Finite Element Method for Stress-Induced Voiding

  • Cher Ming Tan
  • Zhenghao Gan
  • Wei Li
  • Yuejin Hou
Part of the Springer Series in Reliability Engineering book series (RELIABILITY)


With the basic physics of stress-induced voiding (SIV) introduced in Chap. 2, the detailed finite element modeling of the mechanisms of SIV in Cu interconnect will be described here. The understanding of the voiding mechanism through the modeling can certainly shed light on the future design and process improvement of the multilevel interconnect structures. The most widely used commercial finite element software for finite element analysis is ANSYS or ABAQUS.


Stress Gradient Hydrostatic Stress Void Growth Finite Element Method Model Finite Element Method Simulation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    ANSYS Theory Reference (1999) Release 5.6. Swanson Analysis system, Inc. (now ANSYS Inc.), Canosburg, USAGoogle Scholar
  2. 2.
    Rhee SH, Du Y, Ho PS (2003) Thermal stress characteristics of Cu/oxide and Cu/low-k submicron interconnect structures. J Appl Phys 93:3926–3933CrossRefGoogle Scholar
  3. 3.
    Tan CM, Gan ZH, Gao XF (2003) Temperature and stress distribution in the SOI structure during fabrication. IEEE Trans Semicond Manufactur 16:314–318CrossRefGoogle Scholar
  4. 4.
    Zhao JH, Ryan T, Ho PS, Mckerrow AJ, Shih W-Y (1999) Measurement of elastic modulus, Poisson ratio, and coefficient of thermal expansion of on-wafer submicron films. J Appl Phys 85:6421–6424CrossRefGoogle Scholar
  5. 5.
    Grill A (2003) Plasma enhanced chemical vapor deposited SiCOH dielectrics: from low-k to extreme low-k interconnect materials. J Appl Phys 93:1785CrossRefGoogle Scholar
  6. 6.
    Paik JM, Park H, Joo YC (2004) Effect of low-k dielectric on stress and stress-induced damage in Cu interconnects. Microelectron Eng 71:348–357CrossRefGoogle Scholar
  7. 7.
    CRC Handbook of Materials Science (1975) vol II, CRC Press, Boca RatonGoogle Scholar
  8. 8.
    Zhao JH, Du Y, Morgen M, Ho PS (2000) Simultaneous measurement of Young’s modulus, Poisson ratio, and coefficient of thermal expansion of thin films on substrates. J Appl Phys 87:1575–1577CrossRefGoogle Scholar
  9. 9.
    Brandes EA (1999) Smithells metals reference book. 7th edn. Butterworth-Heinemann, OxfordGoogle Scholar
  10. 10.
    Gan ZH, Shao W, Mhaisalkar SG, Chen Z, Li HY (2006) The influence of temperature and dielectric materials on stress induced voiding in Cu dual damascene interconnects. Thin Solid Films 504:161–165CrossRefGoogle Scholar
  11. 11.
    Shi LT, Tu KN (1994) Finite-element modeling of stress distribution and migration in interconnecting studs of a three-dimensional multilevel device structure. Appl Phys Lett 65:1516–1518CrossRefGoogle Scholar
  12. 12.
    Ogawa ET, Mcpherson JW, Rosal JA (2002) Stress-induced voiding under vias connected to wide Cu metal leads In: 40th annual IEEE international reliability physics symposium (IRPS) Proceedings, pp 312–321Google Scholar
  13. 13.
    Li B, Sullivan TD, Lee TC, Badami D (2004) Reliability challenges for copper interconnect. Microelectron Reliab 44:365–380CrossRefGoogle Scholar
  14. 14.
    Kawano M, Fukase T, Yamamoto Y (2003) Stress relaxation in dual-damascene Cu interconnects to suppress stress-induced voiding. In: IEEE international interconnect technology conference, pp 210–212Google Scholar
  15. 15.
    Dieter GE (2001) Elements of the theory of plasticity. McGraw-Hill, LondonGoogle Scholar
  16. 16.
    Nix WD, Arzt E (1992) On void nucleation and growth in metal interconnect lines under electromigration conditions. Metallur Mater Trans A 23:2007–2013CrossRefGoogle Scholar
  17. 17.
    Clement BM, Nix WD, Gleixner RJ (1997) Void nucleation on a contaminated patch. J Mater Res 12:2038–2042CrossRefGoogle Scholar
  18. 18.
    Glasow AV, Fischer AH, Hierlemann M, Penka S, Ungar F (2002) Geometrical aspects of stress-induced voiding in copper interconnects. In: Advanced metallization conference (AMC), pp 161–167Google Scholar
  19. 19.
    Park YB, Jeon IS (2004) Effects of mechanical stress at no current stressed area on electromigration reliability of multilevel interconnects. Microelectron Engineering 71:76–89CrossRefGoogle Scholar
  20. 20.
    Okabayashi H (1993) Stress-induced void formation in metallization for integrated circuits. Mater Sci Eng 11:191–241CrossRefGoogle Scholar
  21. 21.
    Lee KD, Ogawa ET, Yoon S, Lu X, Ho PS (2003) Electromigration reliability of dual-damascene Cu/porous methylsilsesquioxane low k interconnects. Appl Phys Lett 82:2032–2034CrossRefGoogle Scholar
  22. 22.
    Webb E, Witt C, Andryuschenko T, Reid J (2004) Integration of thin electroless copper films in copper interconnect metallization. J Appl Electrochem 34:291–300CrossRefGoogle Scholar
  23. 23.
    Hou Y, Tan CM (2009) Comparison of stress-induced voiding phenomena in copper line-via structures with different dielectric materials. Semicond Sci Technol 24:085014CrossRefMathSciNetGoogle Scholar
  24. 24.
    Shao W, Gan ZH, Mhaisalkar SG, Chen Z, Li HY (2006) The effect of line width on stress-induced voiding in Cu dual damascene interconnects. Thin Solid Films 504:298–301CrossRefGoogle Scholar
  25. 25.
    Yoshida K, Fujimaki T, Miyamoto K, Honma T, Kaneko H, Nakazawa H, Morita M (2002) Stress-induced voiding phenomena for an actual CMOS LSI interconnects. IEDM, IEEE, pp 753–756Google Scholar
  26. 26.
    Hu C-K, Gignac L, Liniger E, Herbst B, Rath DL, Chen ST, Kaldor S, Simon A, Tseng W-T (2003) Comparison of Cu electromigration lifetime in Cu interconnects coated with various caps. Appl Phys Lett 83:869–871CrossRefGoogle Scholar
  27. 27.
    Glasow AV, Fischer AH (2002) New approaches for the assessment of stress-induced voiding in Cu interconnects. In: Proceedings of the IEEE International Interconnect Technology Conference (IITC) pp. 274–276Google Scholar

Copyright information

© Springer-Verlag London Limited  2011

Authors and Affiliations

  • Cher Ming Tan
    • 1
  • Zhenghao Gan
    • 2
  • Wei Li
    • 3
  • Yuejin Hou
    • 1
    • 4
  1. 1.School of Electrical & Electronic EngineeringNanyang Technological UniversitySingaporeSingapore
  2. 2.Technology Research & DevelopmentSemiconductor Manufacturing International (Shanghai) Corp.ShanghaiPeople’s Republic of China
  3. 3.Singapore Institute of Manufacturing TechnologySingaporeSingapore
  4. 4.SingaporeSingapore

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