Although circuit simulators are basically analytical tools, they are ultimately used in the process of circuit synthesis. Circuit synthesis is a complex procedure. One could describe this procedure as a synergy between human inspiration and extensive analytical legwork. SPICE OPUS is the perfect tool for the latter. The simulation examples in this chapter have been selected to emphasize the unique scripting capabilities of SPICE OPUS employed to speed up the tedious legwork – enabling circuit designers to focus on the creative side of their work.
In Sect. 7.1 the power of using parametrized subcircuits is demonstrated by showing how simple and efficient circuit topology reuse can be. Next, in Sect. 7.2, topology switching via the netclass syntax is explained. At the same time, this example shows that any physical (nonelectrical) unit can be seamlessly incorporated in the analysis. Extracting specific (standard) circuit properties is often referred to as taking measurements. This can be efficiently automated, as seen in Sect. 7.3 where some other integrated circuit design specifics are also demonstrated. Section 7.4 goes one step further in this direction, demonstrating techniques for simple handling of design corners. Two important analyses in modern integrated circuit design are addressed in Sects. 7.5 and 7.6: the assessment of device mismatch influence and the prediction of the production yield. So far the examples have dealt with typical analog circuit problems. However, SPICE OPUS can also be used to greatly improve the design of digital and mixed mode building blocks. In Sects. 7.7–7.12 a series of digital circuit phenomena is presented hierarchically, ranging from simple logic gates to complex phase-locked loops.