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Hardware Implementation of Floating-Point Arithmetic

  • Jean-Michel Muller
  • Nicolas Brisebarre
  • Florent de Dinechin
  • Claude-Pierre Jeannerod
  • Vincent Lefèvre
  • Guillaume Melquiond
  • Nathalie Revol
  • Damien Stehlé
  • Serge Torres
Chapter

Abstract

The previous chapter has shown that operations on floating-point numbers are naturally expressed in terms of integer or fixed-point operations on the significand and the exponent. For instance, to obtain the product of two floating-point numbers, one basically multiplies the significands and adds the exponents. However, obtaining the correct rounding of the result may require considerable design effort and the use of nonarithmetic primitives such as leading-zero counters and shifters. This chapter details the implementation of these algorithms in hardware, using digital logic.

Keywords

Critical Path Hardware Implementation Close Path Full Adder Critical Path Delay 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Birkhäuser Boston 2010

Authors and Affiliations

  • Jean-Michel Muller
    • 1
  • Nicolas Brisebarre
    • 1
  • Florent de Dinechin
    • 2
  • Claude-Pierre Jeannerod
    • 3
  • Vincent Lefèvre
    • 3
  • Guillaume Melquiond
    • 4
  • Nathalie Revol
    • 3
  • Damien Stehlé
    • 5
  • Serge Torres
    • 2
  1. 1.CNRS, Laboratoire LIPÉcole Normale Supérieure de LyonLyon Cedex 07France
  2. 2.ENSL, Laboratoire LIPÉcole Normale Supérieure de LyonLyon Cedex 07France
  3. 3.INRIA, Laboratoire LIPÉcole Normale Supérieure de LyonLyon Cedex 07France
  4. 4.INRIA Saclay – Île-de- FranceParc Orsay UniversitéOrsay CedexFrance
  5. 5.CNRSMacquarie University, and University of Sydney School of Mathematics and Statistics University of SydneySydneyAustralia

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