Scheduling for Reduced CPU Energy

  • Mark Weiser
  • Brent Welch
  • Alan Demers
  • Scott Shenker
Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 353)


The energy usage of computer systems is becoming more important, especially for battery operated systems. Displays, disks, and cpus, in that order, use the most energy. Reducing the energy used by displays and disks has been studied elsewhere; this paper considers a new method for reducing the energy used by the cpu. We introduce a new metric for cpu energy performance, millions-of-instructions-per-joule (MIPJ). We examine a class of methods to reduce MIPJ that are characterized by dynamic control of system clock speed by the operating system scheduler. Reducing clock speed alone does not reduce MIPJ, since to do the same work the system must run longer. However, a number of methods are available for reducing energy with reduced clock-speed, such as reducing the voltage [2] [5] or using reversible [7] or adiabatic logic [1]. What are the right scheduling algorithms for taking advantage of reduced clock-speed, especially in the presence of applications demanding ever more instructions-per-second? We consider several methods for varying the clock speed dynamically under control of the operating system, and examine the performance of these methods against workstation traces. The primary result is that by adjusting the clock speed at a fine grain, substantial CPU energy can be saved with a limited impact on performance.


Energy Saving Schedule Algorithm Idle Time Power Saving Clock Rate 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. [1]
    William C. Athas, Jeffrey G. Roller, and Lars “J.” Svensson. “An Energy-Efficient CMOS Line Driver Using Adiabatic Switching”, 1994 IEEE Fourth Great Lakes Symposium on VLSI, pp. 196–199, March 1994.Google Scholar
  2. [2]
    A. P. Chandrakasan and S. Sheng and R. W. Brodersen. “Low-Power CMOS Digital Design”. JSSC, V27,N4, April 1992, pp 473–484.Google Scholar
  3. [3]
    Michael Culbert, “Low Power Hardware for a High Performance PDA”, to appear Proc. of the 1994 Computer Conference, San Francisco.Google Scholar
  4. [4]
    Fred Douglis, P. Krishnan, Brian Marsh, “Thwarting the Power-Hungry Disk”, Proc. of Winter 1994 USENIX Conference, January 1994, pp 293–306Google Scholar
  5. [5]
    Mark A. Horowitz. “Self-Clocked Structures for Low Power Systems”. ARPA semi-annual report, December 1993. Computer Systems Laboratory, Stanford University.Google Scholar
  6. [6]
    Kester Li, Roger Kumpf, Paul Horton, Thomas Anderson, “A Quantitative Analysis of Disk Drive Power Management in Portable Computers”, Proc. of Winter 1994 USENIX Conference, January 1994, pp 279–292.Google Scholar
  7. [7]
    S. Younis and T. Knight. “Practical Implementation of Charge Recovering Asymptotically Zero Power CMOS.” 1993 Symposium on Integrated Systems (C. Ebeling and G. Borriello, eds.), Univ. of Washington, 1993.Google Scholar
  8. [8]
    Wilkes, John “Idleness is not Sloth”, to appear, proc. of the 1995 Winter USENIX ConfGoogle Scholar

Copyright information

© USENIX Association 1994

Authors and Affiliations

  • Mark Weiser
    • 1
  • Brent Welch
    • 2
  • Alan Demers
    • 1
  • Scott Shenker
    • 1
  1. 1.Xerox Palo Alto Research CenterPalo Alto
  2. 2.Sun Microsystems LaboratoryMountain View

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