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Design of Self-Checking Processors Using Efficient Berger Check Prediction Logic

  • T. R. N. Rao
  • Gui-Liang Feng
  • Mahadev S. Kolluru
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Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 285)

Abstract

Processors with concurrent error detection (CED) capability are called self-checking processors. CED is a very important and necessary feature in VLSI microprocessors that are integral and ultradependable for real-time applications. The design of self-checking reduced instruction set computer (RISC) requires the state-of-the-art techniques in computer architectures, implementation and self-checking designs.

Among the components of a processor, the most difficult circuits to check are the arithmetic and logic units (ALUs). In this chapter, we shall concentrate on the design of a self-checking ALU. We introduce a new totally self-checking (TSC) ALU design scheme called Berger check prediction (BCP). Using the BCP, the self-checking processor design can be made very efficient. Also, we discuss the theory involving the use of a reduced Berger code for a more efficient BCP design. A novel design for a Berger code checker based on a generalized code partitioning scheme is discussed here, and is used to efficiently implement the Berger code checking.

Key words

Self-Checking Berger Code Berger Code Partitioning Fault-Tolerance Self-Checking ALU BCP Reduced Berger Check 

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Copyright information

© Kluwer Academic Publishers 1994

Authors and Affiliations

  • T. R. N. Rao
    • 1
  • Gui-Liang Feng
    • 1
  • Mahadev S. Kolluru
    • 1
  1. 1.Center for Advanced Computer StudiesUniversity of Southwestern LouisianaLafayette

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