Skip to main content
SpringerLink
Log in

Wafer-Level 3D Integration for ULSI Interconnects

  • Chapter
  • First Online:
Advanced Nanoscale ULSI Interconnects: Fundamentals and Applications

  • 1835 Accesses

Abstract

Three-dimensional (3D) integration in a system-in-a-package (SiP) implementation (packaging-based 3D) is becoming increasingly used in consumer, computer, and communication applications where form factor is critical. In particular, the hand-held market for a growing myriad of voice, data, messaging, and imaging products is enabled by packaging-based 3D integration (i.e., stacking and connecting individual chips). The key drivers are for increased memory capacity and for heterogeneous integration of different IC technologies and functions.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Lu, J.-Q.; Cale, T. S.; and Gutmann, R. J.: Wafer-level three-dimensional hyper-integration technology using dielectric adhesive wafer bonding. In Materials for Information Technology: Devices, Interconnects and Packaging. Zschech, E.; Whelan, C.; and Mikolajick, T. (eds.), Springer-Verlag, 386 (2005)

    Google Scholar 

  2. Meindl, J. D.; Venkatesan, R.; Davis, J. A.; Joyner, J. W.; Naeemi, A.; Zarkesh-Ha, P.; Bakir, M.; Mulé, T.; Kohl, P. A.; and K. P. Martin: Interconnecting Device Opportunities for Gigascale Integration (GSI). IEEE 2001 International Electronic Devices Meeting (2001 IEDM), 525 (2001)

    Google Scholar 

  3. Das, S.; Fan, A.; Chen, K.-N.; Tan, C. S.; Checka, N.; and Reif, R.: Technology, performance, and computer-aided design of three-dimensional integrated circuits. In Proceedings of the International Symposium on Physical Design (ISPD’04), 108 (2004)

    Google Scholar 

  4. Walker, J.: Market transition to 3d integration and packaging: density, design, and decisions. In International Conference on 3D Architectures for Semiconductor Integration and Packaging, Tempe, AZ (2005)

    Google Scholar 

  5. Carson, F.: 3D SiP: established and emerging trends. In Preconference Symposium of the 3rd International Conference on 3D Architectures for Semiconductor Integration and Packaging, Burlingame, CA (2006)

    Google Scholar 

  6. Tessler, T.: Recent development in wafer level packaging. In 3rd IC Packaging Technology Exposition and Conference, Japan (2002)

    Google Scholar 

  7. Savastiouk, S., Siniaguine, O., and Korczynski, E.: 3D Wafer level packaging. In 2000 International Conference on High-Density Interconnect and Systems Packaging (2000)

    Google Scholar 

  8. Morrow, P.; Park, C.-M.; Ramanathan, S.; Kobrinsky, M. J.; and Harmes, M.: Three-dimensional wafer stacking Via Cu-Cu bonding integrated with 65-nm Strained-Si/Low-k CMOS technology. IEEE Electron Device Lett. 27(5), 335 (2006)

    Article  CAS  Google Scholar 

  9. Patti, R.: Three-dimensional integrated circuits and the future of system-on-chip designs. Proc. IEEE 94(6), 1214 (2006)

    Article  Google Scholar 

  10. Lu, J.-Q.; Jindal, A.; Kwon, Y.; McMahon, J. J.; Lee, K.-W.; Kraft, R. P.; Altemus, B.; Cheng, D.; Eisenbraun, E.; Cale, T. S.; and Gutmann, R. J.; 3D System-on-a-chip using dielectric glue bonding and Cu Damascene inter-wafer interconnects. In Thin Film Materials, Processes, and Reliability, Mathad, S. et al. (Eds.), ECS Proc. PV 2003–13, 381–389 (2003)

    Google Scholar 

  11. McMahon, J. J.; Lu, J.-Q.; and Gutmann, R. J.: Wafer bonding of damascene-patterned metal/adhesive redistribution layers for via-first three-dimensional (3D) interconnect. In IEEE 55th Electronic Components and Technology Conference (ECTC 2005), 331 (2005)

    Google Scholar 

  12. Guarini, K. W.; Topol, A. W.; Ieong, M. R.; Yu, Shi, L.; Newport, M. R.; Frank, D. J.; Singh, D. V.; Cohen, G. M.; Nitta, S. V.; Boyd, D. C.; O’Neil, P. A.; Tempest, S. L.; Pogge, H. B.; Purushothaman, S.; and Haensch, W. E.: Electrical integrity of state-of-the-art 0.13 μm SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication. In Digest of International Electron Device Meeting, 943 (2002)

    Google Scholar 

  13. Burns, J.; Aull, B.; Chen, C.; Chen, C.-L.; Keast, C.; Knecht, C. J.; Suntharalingam, V.; Warner, K.; Wyatt, W. P.; and Yost, D.-R.: A wafer-scale 3-D circuit integration technology. IEEE Trans. Electron Devices 53(10), 2507 (2006)

    Article  Google Scholar 

  14. Ramm, P.; Bonfert, D.; Gieser, Haufe, H. J.; Iberl, F.; Klumpp, A.; Kux, A.; Wieland, R.: InterChip via technology for vertical system integration. 2001 IEEE International Interconnect Technology Conference (IITC), 160 (2001)

    Google Scholar 

  15. Lee, K. W.; Nakamura, T.; One, T.; Yamada, Y.; Mizukusa, T.; Hasimoto, H.; Park, K. T.; Kurino, H.; and Koyanagi, M.: Three-dimensional shared memory fabricated using wafer stacking technology. In IEEE 2000 International Electron Devices Meeting (2000 IEDM), 165 (2000)

    Google Scholar 

  16. Markunas, B.: 3D Architectures for semiconductor integration and packaging. In International Conference on 3D Architectures for Semiconductor Integration and Packaging, Burlingame, CA (2004)

    Google Scholar 

  17. Gann, K.: Neo-stacking technology. High Density Interconnect Magazine 2 (1999)

    Google Scholar 

  18. Goldstein, H.: Packages go vertical. IEEE Spectr. 38(8), 46 (2001)

    Article  Google Scholar 

  19. Lowton, G.: The lowdown on high-rise chips. In Computer magazine, IEEE Comput. Soc., 24 (2004)

    Google Scholar 

  20. Souri, S. J. and Saraswat, K. C.: Interconnect performance modeling for 3D integrated circuits with multiple Si layers. IEEE International Interconnect Technology Conference (IITC 1999), 24 (1999)

    Google Scholar 

  21. Zeng, A. Y.; Lu,J.-Q.; Rose, K.; and Gutmann, R. J.: First-order performance prediction of cache memory with wafer-level 3D Integration. IEEE Design Test Comput. 22(6), 548 (2005)

    Article  Google Scholar 

  22. Gutmann, R. J.; Zeng, A. Y.; Devarajan, S.; Lu J.-Q.; and Rose, K.: Wafer-level three-dimensional monolithic integration for intelligent wireless terminals. J. Semiconductor Technol. Sci. 4(3), 196–203 (2004)

    Google Scholar 

  23. Lu, J.-Q.; Devarajan, S.; Zeng, A. Y.; Rose, K.; and Gutmann, R. J.: Die-on-wafer and wafer level three-dimensional (3D) integration of heterogeneous IC technologies for RF-microwave-millimeter applications. In Materials, Integration and Packaging Issues for High-Frequency Devices II. Cho, Y. S.; Shiffler, D.; Ranall, C. A.; Tilmans, H. A. C.; and Tsurumi T. (eds.) MRS Proc. 833, 229–234 (2004)

    Google Scholar 

  24. Lu, J.-Q.; Sun, J.; Giuliano D.; and Gutmann, R. J.: 3D architecture for power delivery to microprocessors and ASICs. In Proceedings CD of the 3rd International Conference on 3D Architectures for Semiconductor Integration and Packaging, Burlingame, CA (2006)

    Google Scholar 

  25. Sun, J.; Lu, J.-Q.; Giuliano, D.; Chow, T. P.; Gutmann, R. J.: 3D power delivery for microprocessors and high-performance ASICs. 22nd Annual IEEE Applied Power Electronics Conference and Exposition (APEC 2007), 127 (2007)

    Google Scholar 

  26. Suntharalingam, V.; Berger, R.; Burns, J.; Chen, C.; Keast, C.; Knecht, J.; Lambert, R.; Newcomb, K.; O’Mara, D.; Rathman, D.; Shaver, D.; Soares, A.; Stevenson, C.; Tyrell, B.; Warner, K.; Wheeler, B.; Yost, D.; and Young D.: Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology. In Proceedings of the IEEE International Solid-State Circuits Conference, 356 (2005)

    Google Scholar 

  27. Temple, D.; Bower, C. A.; Malta, D.; Robinson, J. E.; Coffman, P. R.; Skokan M. R.; and Welch, T. B.: High density 3-D integration technology for massively parallel signal processing in advanced infrared focal plane array sensors. In Digest of 2006 IEEE International Electron Device Meeting (2006 IEDM), 143 (2006)

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. RPI, Low Center for Industrial Innovation, 12180, Troy, New York, USA

    Ronald J. Gutmann & Jian-Qiang Lu

Authors
  1. Ronald J. Gutmann
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Jian-Qiang Lu
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Ronald J. Gutmann .

Editor information

Editors and Affiliations

  1. Tel Aviv University, Ramat Aviv, Tel Aviv, 69978, Israel

    Yosi Shacham-Diamand

  2. Dept. Applied Chemistry, Waseda University, Okubo 3-4-1 , Tokyo, 169-8555, Japan

    Tetsuya Osaka

  3. Emerson Network Power, Cooligy Precision Cooling, Maude Avenue 800, Mountain View, 94043, U.S.A.

    Madhav Datta

  4. Division of Corporate Relations, The University of Tokyo, Hongo 7-3-1, Tokyo , 113-8654, Japan

    Takayuki Ohba

Rights and permissions

Reprints and permissions

Copyright information

© 2009 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Gutmann, R.J., Lu, JQ. (2009). Wafer-Level 3D Integration for ULSI Interconnects. In: Shacham-Diamand, Y., Osaka , T., Datta, M., Ohba, T. (eds) Advanced Nanoscale ULSI Interconnects: Fundamentals and Applications. Springer, New York, NY. https://doi.org/10.1007/978-0-387-95868-2_6

Download citation

Publish with us

Policies and ethics

Search

Navigation