Wafer-Level 3D Integration for ULSI Interconnects



Three-dimensional (3D) integration in a system-in-a-package (SiP) implementation (packaging-based 3D) is becoming increasingly used in consumer, computer, and communication applications where form factor is critical. In particular, the hand-held market for a growing myriad of voice, data, messaging, and imaging products is enabled by packaging-based 3D integration (i.e., stacking and connecting individual chips). The key drivers are for increased memory capacity and for heterogeneous integration of different IC technologies and functions.


Wafer Bonding Epitaxial Lateral Overgrowth Signal Processing Electronic Heterogeneous Integration Vertical Interconnectivity 
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Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  1. 1.RPILow Center for Industrial InnovationTroyUSA

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