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Emerging Nanoscale Interconnect Processing Technologies: Fundamental and Practice

  • Alain E. Kaloyeros
  • James Castracane
  • Kathleen Dunn
  • Eric Eisenbraun
  • Anand Gadre
  • Vincent LaBella
  • Timothy Stoner
  • Bai Xu
  • James G. Ryan
  • Anna Topol
Chapter

Abstract

The prospects for Gigascale integration and beyond are hindered, in the near term, by increasingly higher RC delays in global and semi-global electrical interconnect systems. Long-term, signal transmission delays are projected to become significantly more challenging due to fundamental limits imposed by the basic laws of physics. As feature sizes shrink below the mean free path for electron scattering in conventional metal wires, surface scattering, which is defined as the scattering of electron waves from the boundaries of ultra narrow conductors, severely hinders electronic conductivity and stands as a major roadblock to Moore’s Law at the most fundamental level.

Keywords

Atomic Layer Deposition Chemical Mechanical Polishing Electroless Plating Wafer Level Copper Interconnect 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  • Alain E. Kaloyeros
    • 1
  • James Castracane
    • 1
  • Kathleen Dunn
    • 1
  • Eric Eisenbraun
    • 1
  • Anand Gadre
    • 1
  • Vincent LaBella
    • 1
  • Timothy Stoner
    • 1
  • Bai Xu
    • 1
  • James G. Ryan
    • 2
  • Anna Topol
    • 3
  1. 1.College of Nanoscale Science and EngineeringThe University at Albany-SUNYAlbanyUSA
  2. 2.Dean, JSNNGreensboroUSA
  3. 3.IBM T. J. Watson Research CenterYorktown HeightsUSA

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