Advanced Planarization Techniques

  • Bulent M. BasolEmail author


As the integrated circuit technology nodes reach 45 nm and beyondgrowing requirement for reduced propagation delay dictates inclusion of low-k materials in the interconnect metallization structures. Unfortunately, mechanical properties, such as hardness and Young’s modulus of the dielectric materials, deteriorate as their porosity is increased and the k value is reduced to 2.5 and below [1]. Reliability issues such as electromigration, stress migration, and time-dependent dielectric breakdown (TDDB) lifetimes are also becoming more challenging for multi-stack low-k structures. The low-k and ultra low-k materials are prone to delamination [2] and cracking [3] during CMP; risk of damage rising as the polishing pressure and time increases [4]. It has been demonstrated that delamination in low-k stacks was driven by the work done against the friction force during the CMP process [5]. Therefore, it is becoming more and more difficult to polish and planarize topographic copper layers, deposited on low-k dielectric materials, at low stress and high rate while maintaining the mechanical integrity of the overall interconnect structure. Furthermore as feature widths and depths shrink, tolerances for metal loss and line resistance variation over the wafer surface are also reduced. In advanced interconnects, adding sacrificial thickness to the dielectric layer which can then be removed during CMP overpolish step is not a good option to minimize topography because hard cap layers are often used to protect the low-k dielectric materials from the negative effects of CMP [6, 7] and thickness of these layers is kept to a minimum to reduce their contribution to the effective dielectric constant of the stack. Therefore, as technology nodes move beyond 45 nm, planarization steps of the interconnect manufacturing process flow are expected to offer reduced stress, higher planarization efficiency, reduced copper dishing, less dielectric erosion, better global line resistance uniformity, while at the same time maintaining high process throughput, low defectivity, and low cost.


Copper Surface Step Height Wafer Surface Copper Layer Copper Film 
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© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  1. 1.SoloPower Inc.San JoseUSA

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