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Lithography for Cu Damascene Fabrication

  • Yoshihiro Hayashi
Chapter

Abstract

As CMOS transistors are scaled down, interconnects to link them are also shrunk to reduce the line pitches [1, 2]. Figure 20.1a shows the technology trends of the CMOS gate length (Lg) and the minimum line pitches (P int). In 130 nm node LSIs, the Lg and P int have been approximately 100 and 400 nm, respectively. By device scaling, Lg and P int in 45 nm node LSIs will be shrunk to 40–50 and 140 nm, respectively. These small features are patterned by photo-lithography process, in which photo-sensitive resist is coated on silicon wafer and is exposed by laser light. The resist is developed to make fine patterns of the resist. Figure 20.1b shows trends of the minimum pattern resolution (R) and the depth of focus (DOF). To reduce the resolution, the wavelength of exposure light should be shortened using the large diameter lens (NA number), however the DOF decreases drastically. This requires flat-surface interconnects such as Cu Damascene interconnects for multi-level stacks.

Keywords

Oxygen Plasma Hard Mask CMOS Transistor Barrier Metal Line Edge Roughness 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgments

The author would like to acknowledge Drs. F. Ito, H. Ohtake (now in Tohoku University), J. Kawahara, N. Inoue, M. Tagami, M. Tada (now in NEC), M. Ueki, K. Hijioka, M. Abe, T. Takeuchi, T. Onodera, S. Saito, and N, Furutake all in LSI Fundamental Research Laboratory for research on advanced LSI BEOL technologies.

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Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  1. 1.ULSI Fundamental Research Laboratory, Microelectronics Research LaboratoriesNEC Electronics CorporationSagamiharaJapan

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