Introduction to Electrochemical Process Integration for Cu Interconnects

  • Takayuki OhbaEmail author


This chapter focuses on advanced multilevel interconnects, contributed by distinguished authors in the following sections: Damascene Concept and Process Steps (Nobuyoshi Kobayashi), Advanced BEOL Technology Overview (Takashi Yoda and Hideshi Miyajima), Lithography for Cu Damascene fabrication (Yoshihiro Hayashi), Physical Vapor Deposition Barriers for Cu metallization PVD Barriers (Junichi Koike), Low-k dielectrics (Yoshihiro Hayashi), CMP for Cu Processing (Manabu Tsujimura), Electrochemical View of Copper Chemical Mechanical Polishing (CMP) (D. Starosvetsky and Y. Ein-Eli), and Copper Post-CMP Cleaning (D. Starosvetsky and Y. Ein-Eli).


Barrier Layer Chemical Mechanical Polishing Chemical Mechanical Polishing Process Distinguished Author Damascene Process 
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  1. 1.
    Ohba, T.: Multilevel Interconnect Technologies in SoC and SiP for 100-nm Node and Beyond. Proc. of IEEE 6th International Conf. on Solid-State Integrated Circuit Technol. (ICSICT), Bing-Zong Li et al. Eds. 46 (2001)Google Scholar
  2. 2.
    Sakurai, T.: Interconnection from Design Prospective. Proceedings of Advanced Metallization Conference 2000, Edelstein. D.; Dixit, G.; Yasuda, Y.; and Ohba. T., Eds. Mat. Res. Soc. PA, 53 (2001)Google Scholar
  3. 3.
    Suga, T. and Otsuka, K.: A new era of system integration and packaging. J. Electron. Packaging 13(7), 621 (2000)Google Scholar
  4. 4.
    Bohr, M. T.: Interconnect scaling – The real limiter to high performance ULSI. IEEE IEDM Tech. Dig. 241 (1995)Google Scholar
  5. 5.
    Venkatesan, S.; Gelatos, A. V.; Misra, V.; Smith, B.; Islam, R.; Cope, J.; Wilson, B.; Tuttle, D.; Cardwell, R.; Anderson, S.; Angyal, M.; Bajaj, R.; Cappasso, C.; Crabtree, P.; Das, S.; Farkas, J.; Fiordalice, B.; Freeman, M.; Gilbert, P.V.; Herrick, M.; Jain, A.; Kawasaki, H.; King, C.; Klein, J.; Lii, T.; ReidK.; Saaranen, T.; Simpson, C.; Sparks, T.; Tsui, P.; Venkatraman, R.; Watts, D.; Weitzman, E. J.; Woodruff, R.; Yang, I.; Bhat, N.; Hamilton, G.; and Yu, Y.: A High Performance 1.8 V 0.20 μm CMOS Technology with Copper Metallization. IEEE IEDM Tech. Dig. 769 (1997)Google Scholar
  6. 6.
    Edelstein, D.; Heidenreich, J.; Goldblatt, R.; Cote, W.; Uzoh, C.; Lustig, N.; Roper, P.; McDevitt, T.; Motsiff, W.; Simon, A.; Dukovuc, J.; Wachnik, E.; Rathore, H.; Schultz, R.; Su, L.; Luce, S.; and Slattery, J.: Full Copper Wiring in a sub-0.25 μm CMOS ULSI Technology. IEEE IEDM Tech. Dig. 773 (1997)Google Scholar
  7. 7.
    Masu, K.: GHz Interconnect in ULSI, Technical Report of IEICE. The Inst. of Electronics. Inf. Commun. Eng. 101(1), 87 (2001)Google Scholar
  8. 8.
    Misawa, N.; Ohba, T.; and Yagi, H.: Planarized copper multilevel interconnections for ULSI applications. MRS Bull. XIX 8, 63 (1994)Google Scholar
  9. 9.
    Kaanta, C. W.; Bombardier, S. G.; Cote, W. J.; Hill, W. R.; Kerszykowski, G.; Landis, H. S.; Poindexter, D. J.; Pollard, C. W.; Ross, G. H.; Ryan, J. G.; Wolff, S.; and Cronin, J. E.: Dual Damascene: A ULSI Wiring Technology. Proc. of 8th Int. IEEE VLSI Multilevel Interconnection Conf. 144 (1991)Google Scholar
  10. 10.
    Kudo, H.; Yoshie, K.; Yamaguchi, S.; Watanabe, K.; Ikeda, M.; Kakamu, K.; Hosoda, T.; Ohhira, K.; Santoh, N.; Misawa, N.; Matsuno, K.; Wakasugi, Y.; Hasegawa, A.; Nagase, K.; and Suzuki, T.: Copper Dual Damascene Interconnects with Very Low-k Dielectrics Targeting for 130 nm Node. Proc. of IEEE Int. Interconnects Conf. (IITC) 270 (2000)Google Scholar
  11. 11.
    Ohba, T.: A Study of Current Multilevel Interconnect Technologies for 90 nm Nodes and Beyond, Fujitsu Sci. Tech. J. 13 (2002)Google Scholar
  12. 12.
    Nakai, S.; Kojima, M.; Misawa, N.; Miyajima, M.; Asai, S.; Inagaki, S.; Iba, Y.; Ohba, T.; Kase, M.; Kitada, H.; Satoh, S.; Shimizu, N.; Sugiura, I.; Sugimoto, F.; Setta, Y.; Tanaka, T.; Tamura, N.; Nakaishi, M.; Nakata, Y.; Nakahira, J.; Nishikawa, N.; Hasegawa, A.; Fukuyama, S.; Fujita, K.; Hosaka, K.; Horiguchi, N.; Matsuyama, H.; Minami, T.; Minamizawa, M.; Morioka, H.; Yano, E.; Yamaguchi, A.; Watanabe, K.; Nakamura, T.; and Sugii, T.: A 65 nm CMOS Technology with a High-Performance and Low-Leakage Transistor (A 0.55-μm2 6T-SRAM Cell and Robust Hybrid-ULK/Cu interconnects for Mobile Multimedia Applications). IEEE IEDM Tech. Dig. 285 (2003)Google Scholar
  13. 13.
    Dubin, V. M.; Shacham-DiamandY.; Zhao, B.; Vasudev, P. K.; and Ting, C. H.: Selective and blanket electroless copper deposition for ultralarge scale integration. J. Electrochem. Soc. 144, 898 (1997)CrossRefGoogle Scholar

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© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  1. 1.The University of TokyoTokyoJapan

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