Advertisement

Electrical and Mechanical Characteristics of Air-Bridge Cu Interconnects

  • Hyun Park
  • Matthias Kraatz
  • Jay Im
  • Bernd Kastenmeier
  • Paul S. Ho
Chapter

Abstract

As Cu/low-k technology continues to advance, extensive efforts are being focused to implement ultra-lower k dielectrics for future interconnects. For the 45 nm node, the interconnect structure is required to have an effective dielectric constant of 2.3–2.6 [1], which will require the dielectric material to have a bulk dielectric constant of about 2.1 if no air-gap design is considered.

Keywords

Dielectric Material Hydrostatic Stress Effective Permittivity Effective Elastic Modulus Effective Dielectric Constant 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgments

This work was supported by SEMATECH through the Advanced Materials Research Center at the University of Texas at Austin and the Korea Research Foundation Grant funded by Korea Government (MOEHRD, Basic Research Promotion Fund) (KRF-2004-214-D00312).

References

  1. 1.
    ITRS 2004 Update: Interconnect.Google Scholar
  2. 2.
    Arnal, V. et al.: Integration of a 3 level Cu-SiO2 air gap interconnect for sub 0.1 micron CMOS technologies (Proc., IEEE IITC) 298 (2001)Google Scholar
  3. 3.
    Shieh, P. et al.: Electromigration reliability of low capacitance air-gap interconnect structures (Proc. IEEE IITC) 203 (2002)Google Scholar
  4. 4.
    Gabric, Z. et al.: Air gap technology by selective ozone/TEOS deposition (Proc. IEEE IITC) 151 (2004)Google Scholar
  5. 5.
    Noguchi, J. et al.: Simple self-aligned air-gap process with Cu/FSG structure (Proc., IEEE IITC) 68 (2003)Google Scholar
  6. 6.
    Uno, S. et al.: Dual-Damascene process for air-gap Cu interconnects using conventional CVD films as sacrificial layers (Proc., IEEE IITC) 174 (2005)Google Scholar
  7. 7.
    Daamen, R. et al.: Air gap integration for the 45 nm node and beyond (Proc., IEEE IITC) 240 (2005)Google Scholar
  8. 8.
    Yang, K.-H. et al.: Sequential process modeling for determining process-induced thermal stress in advanced Cu/Low-k interconnects (Mater. Res. Soc. Sym Proc.) Vol. 766, 39 (2003)Google Scholar
  9. 9.
    Rhee, S.-H.; Du, Y.; and Ho, P. S.: Thermal stress characteristics of Cu/oxide and Cu/low-k submicron interconnect structures. J. Appl. Phys. 93, 3926 (2003)CrossRefGoogle Scholar
  10. 10.
    Wang, G.: Thermal deformation of electronic packages and packaging effect on reliability for Copper/low-k interconnect structures (Ph.D. Dissertation, The University of Texas at Austin) 56, 60 (2004)Google Scholar
  11. 11.
    Korhonen, M. A. et al.: Stress evolution due to electromigration in confined metal lines. J. Appl. Phys. 73, 3790 (1993).CrossRefGoogle Scholar
  12. 12.
    Hau-Riege, S. P. and Thompson, C. V.: The effects of the mechanical properties of the confinement material on electromigration in metallic interconnects. J. Mater. Res. 15, 1797 (2000)CrossRefGoogle Scholar
  13. 13.
    Gan, D. W.: Thermal stress and stress relaxation in Cu metallization for ULSI interconnects (Ph.D. Dissertation, The University of Texas at Austin, USA) 190, 193 (2005)Google Scholar
  14. 14.
    Kastenmeier, B.; Pfeifer, K.; and Knorr, A.: Porous low-k materials and effective k. Semiconductor Int., 27, 87 (2004)Google Scholar
  15. 15.
    ABAQUS/Standard, User’s Manual, Vol. I, Hibbitt, Karlsson & Sorensen, Inc., 7.4.2Google Scholar
  16. 16.
    Auersperg, J.; Vogel, D.; and Michel; B.: Crack and delamination risk evaluation of thin silicon applications based on fracture mechanics approaches. 5th Int. Conf. on Thermal and Mechanical Simulation and Experiments in Micro-Electronics and Micro-Systems, 169 (2004)Google Scholar
  17. 17.
    Baik, J.-M.; Park, H.; Joo, Y. C.; and Park, K.-C.: Effect of dielectric materials on stress-induced damage modes in Damascene Cu lines. J. Appl. Phys. 97, 104513 (2005)CrossRefGoogle Scholar
  18. 18.
    Wang, G.; Groothuis, S.; and Ho, P. S.: Packaging effect on reliability for Cu/low k structures. IEEE ECTC, 727 (2003)Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  • Hyun Park
    • 1
  • Matthias Kraatz
    • 2
  • Jay Im
    • 2
  • Bernd Kastenmeier
    • 3
  • Paul S. Ho
    • 2
  1. 1.Memory DivisionSamsung Electronics Co., LTDSeoulKorea
  2. 2.Microelectronics Research Center, The University of Texas at AustinAustinUSA
  3. 3.Freescale Semiconductor IncAustinUSA

Personalised recommendations