Timing Verification


This chapter describes the checks that are performed as part of static timing analysis. These checks are intended to exhaustively verify the timing of the design under analysis.

The two primary checks are the setup and hold checks. Once a clock is defined at the clock pin of a flip-flop, setup and hold checks are automatically inferred for the flip-flop. The timing checks are generally performed at multiple conditions including the worst-case slow condition and best-case fast condition. Typically, the worst-case slow condition is critical for setup checks and best-case fast condition is critical for hold checks - though the hold checks may be performed at the worst-case slow condition also.

The examples presented in this chapter assume that the net delays are zero; this is done for simplicity and does not alter the concepts presented herein.


Arrival Time Clock Cycle Timing Verification Clock Tree Data Arrival Time 
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Copyright information

© Springer-Verlag US 2009

Authors and Affiliations

  1. 1.eSilicon CorporationSuite 615 AllentownUSA
  2. 2.eSilicon CorporationNew ProvidenceUSA

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