Configuring the STA Environment

  • J. Bhasker
  • Rakesh Chadha

This chapter describes how to set up the environment for static timing analysis. Specification of correct constraints is important in analyzing STA results. The design environment should be specified accurately so that STA analysis can identify all the timing issues in the design. Preparing for STA involves amongst others, setting up clocks, specifying IO timing characteristics, and specifying false paths and multicycle paths. It is important to understand this chapter thoroughly before proceeding with the next chapter on timing verification.


Output Port Input Port Timing Path Master Clock Source Latency 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag US 2009

Authors and Affiliations

  1. 1.eSilicon CorporationSuite 615 AllentownUSA
  2. 2.eSilicon CorporationNew ProvidenceUSA

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