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Delay Calculation

  • J. Bhasker
  • Rakesh Chadha
Chapter

This chapter provides an overview of the delay calculation of cellbased designs for the pre-layout and post-layout timing verification. The previous chapters have focused on the modeling of the interconnect and the cell library. The cell and interconnect modeling techniques are utilized to obtain timing of the design.

Keywords

Path Delay Timing Path Effective Capacitance Delay Calculation Driving Cell 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag US 2009

Authors and Affiliations

  1. 1.eSilicon CorporationSuite 615 AllentownUSA
  2. 2.eSilicon CorporationNew ProvidenceUSA

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