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Interconnect Parasitics

  • J. Bhasker
  • Rakesh Chadha
Chapter

This chapter provides an overview of various techniques for handling and representing interconnect parasitics for timing verification of the designs. In digital designs, a wire connecting pins of standard cells and blocks is referred to as a net. A net typically has only one driver while it can drive a number of fanout cells or blocks. After physical implementation, the net can travel on multiple metal layers of the chip. Various metal layers can have different resistance and capacitance values. For equivalent electrical representation, a net is typically broken up into segments with each segment represented by equivalent parasitics. We refer to an interconnect trace as a synonym to a segment, that is, it is part of a net on a specific metal layer.

Keywords

Metal Layer File Size Area Overhead Timing Verification Cell Library 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag US 2009

Authors and Affiliations

  1. 1.eSilicon CorporationSuite 615 AllentownUSA
  2. 2.eSilicon CorporationNew ProvidenceUSA

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