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Robust Verification

  • J. Bhasker
  • Rakesh Chadha
Chapter

This chapter describes special STA analyses such as time borrowing, clock gating and non-sequential timing checks. In addition, advanced STA concepts such as on-chip variations, statistical timing and tradeoff between power and timing are also presented.

Keywords

Path Delay Gating Signal Clock Tree Clock Gating Data Arrival Time 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag US 2009

Authors and Affiliations

  1. 1.eSilicon CorporationSuite 615 AllentownUSA
  2. 2.eSilicon CorporationNew ProvidenceUSA

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