• J. Bhasker
  • Rakesh Chadha

This chapter provides an overview of the static timing analysis procedures for nanometer designs. This chapter addresses questions such as, what is static timing analysis, what is the impact of noise and crosstalk, how these analyses are used and during which phase of the overall design process are these analyses applicable.


Finite State Machine Physical Design Clock Tree Timing Check Logic Optimization 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag US 2009

Authors and Affiliations

  1. 1.eSilicon CorporationSuite 615 AllentownUSA
  2. 2.eSilicon CorporationNew ProvidenceUSA

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