Statistical and Numerical Approach for a Computer efficient circuit yield analysis

  • Lucas Brusamarello
  • Roberto da Silva
  • Gilson I. Wirth
  • Ricardo Reis
Part of the IFIP International Federation for Information Processing book series (IFIPAICT, volume 291)

In nanometer scale CMOS parameter variations are a challenge for the design of high yield integrated circuits. Statistical Timing Analysis techniques require statistical modeling of logic blocks in the netlist in order to compute mean and standard deviate for system performance. In this work we propose an accurate and computer efficient methodology for statistical modeling of circuit blocks. Numerical error propagation techniques are applied to model within-die and die-todie process variations at electrical level. The model handles co-variances between parameters and spatial correlation, and gives as output the statistical parameters that can be applied at higher level analysis tools, as for instance statistical timing analysis tools. Moreover, we develop a methodology to compute the quantitative contribution of each circuit random parameter to the circuit performance variance. This methodology can be employed by the designer or by an automatic tool in order to improve circuit yield. The methodology for yield analysis proposed in this work is shown to be a solid alternative to traditional Monte Carlo analysis, reducing by orders of magnitude the number of electrical simulations required to analyze memory cells, logic gates and small combinational blocks at electrical level. As a case study, we model the yield loss of a SRAM memory due to variability in access time, considering variance in threshold voltage, channel width and length, which may present both dieto- die and within-die variations. We compare results obtained using the proposed method with statistical results obtained by Monte Carlo simulation. A speedup of 1000× is achieved, with mean error of the standard deviate being 7% compared to MC.


Error Propagation Access Time Very Large Scale Integration Spice Simulation SRAM Cell 


  1. 1.
    A. Agarwal, D. Blaauw, and V. Zolotov. Statistical timing analysis for intra-die process variations with spatial correlations. In Proc. International Conference on Computer Aided Design, pages 900–907, Nov. 2003.Google Scholar
  2. 2.
    A. Agarwal . A process-tolerant cache architecture for improved yield in nanoscale technologies. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13(1):27–38, 2005.CrossRefGoogle Scholar
  3. 3.
    A. Agarwal . Process variation in embedded memories: failure analysis and variation aware architecture. IEEE Journal of Solid-State Circuits, 40(9):1804–1814, Sept. 2005.CrossRefGoogle Scholar
  4. 4.
    A. Agarwal, B. C. Paul, and K. Roy. Process variation in nano-scale memories: failure analysis and process tolerant architecture. In Proceedings of Custom Integrated Circuits Conference, pages 353–356, 2004.Google Scholar
  5. 5.
    Jacques G. Amar. The monte carlo method in science and engineering. Computing in Science and Engineering, 8(2):9–19, 2006.Google Scholar
  6. 6.
    K. Bernstein, D. J. Frank, A. E. Gattiker, W. Haensch, B. L. Ji, S. R. Nassif, E. J. Nowak, D. J. Pearson, and N. J. Rohrer. High-performance cmos variability in the 65-nm regime and beyond. IBM J. Res. Dev., 50(4/5):433–449, 2006.CrossRefGoogle Scholar
  7. 7.
    Yang Byung-Do and Kim Lee-Sup. A low-power sram using hierarchical bit line and local sense amplifier. IEEE Journal of Solid-State Circuits, 40(6):1366– 1376, June 2005.CrossRefGoogle Scholar
  8. 8.
    Y. Cao et al. New paradigm of predictive mosfet and interconnect modeling for early circuit design. In Proc. Custom Integrated Circuit Conference, pages 201–204, June 2000.Google Scholar
  9. 9.
    B. Cheng, S. Roy, G. Roy, F. Adamu-Lema, and A. Asenov. Impact of intrinsic parameter fluctuations in decanano mosfets on yield and functionality of sram cells. Solid-State Electronics, 49(5):740, 2005.CrossRefGoogle Scholar
  10. 10.
    Kim Hyun-Woo et al. Experimental investigation of the impact of lwr on sub- 100-nm device performance. IEEE Transactions on Electron Devices, 51(12):1984– 1988, Dec. 2004.Google Scholar
  11. 11.
    ITRS. International Technology Roadmap for Semiconductors, 2005. Available at ¡¿. Visited on Nov. 2006.
  12. 12.
    Kunhyuk Kang, B. C. Paul, and K. Roy. Statistical timing analysis using levelized covariance propagation. In Proceedings Design, Automation and Test in Europe, pages 764–769 Vol. 2, 2005.Google Scholar
  13. 13.
    H. Mahmoodi, S. Mukhopadhyay, and K. Roy. Estimation of delay variations due to random-dopant fluctuations in nanoscale cmos circuits. IEEE Journal of Solid-State Circuits, 40(9): 1787–1796, 2005.CrossRefGoogle Scholar
  14. 14.
    S. Mukhopadhyay, H. Mahmoodi, and K. Roy. Statistical design and optimization of sram cell for yield enhancement. In Proc. IEEE/ACM International Conference on Computer Aided Design, pages 10–13, Nov. 2004.Google Scholar
  15. 15.
    S. Mukhopadhyay, H. Mahmoodi-Meimand, and K. Roy. Modeling and estimation of failure probability due to parameter variations in nano-scale srams for yield enhancement. In Proc. Symposium on VLSI Circuits, pages 64–67, Piscataway, NJ, June 2004.Google Scholar
  16. 16.
    N. S. Nagaraj et al. Beol variability and impact on rc extraction. In Proc. Design Automation Conference, pages 758–759, Anaheim, California, USA, June 2005.Google Scholar
  17. 17.
    Lawrence W. Nagel. SPICE2: A Computer Program to Simulate Semiconductor Circuits. University of California, Electronics Research Laboratory, College of Engineering, Berkeley, CA, 1975.Google Scholar
  18. 18.
    Sani R. Nassif. Modeling and forecasting of manufacturing variations. In Proc. International Workshop on Statistical Metrology, 2000.Google Scholar
  19. 19.
    S.R Nassif. Design for variability in dsm technologies [deep submicron technologies]. In Proc. IEEE International Symposium on Quality Electronic Design, pages 451–454, 2000.Google Scholar
  20. 20.
    M. Orshansky . Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 21(5):544–553, 2002.CrossRefGoogle Scholar
  21. 21.
    L. G. Parrat. Probability and Experimental Errors on Science. John Wiley and Sons, New York, NY, USA, 1961.Google Scholar
  22. 22.
    Rajeev R. Rao et al. Parametric yield estimation considering leakage variability. In Proc. Design Automation Conference, 41., pages 442–447, 2004.Google Scholar
  23. 23.
    SYNOPSYS INC. HSPICE Simulation and Analysis User Guide, 2005.Google Scholar
  24. 24.
    Yuan Taur. Cmos scaling into the nanometer regime. Proceedings of the IEEE, 85(4):486–504, Apr. 1997.CrossRefGoogle Scholar
  25. 25.
    Yuan Taur and Tak H. Ning. Fundamentals of modern VLSI devices. Cambridge University Press, New York, NY, USA, 1998.Google Scholar
  26. 26.
    Chandu Visweswariah. Death, taxes and failing chips. In Proc. Design and Automation Conference, DAC, 40., pages 343–347, Anaheim, CA, USA, 2003. New York: ACM Press.Google Scholar
  27. 27.
    P. S. Zuchowski et al. Process and environmental variation impacts on asic timing. In Proc. IEEE/ACM International Conference on Computer Aided Design, ICCAD, pages 336–342, 2004.Google Scholar

Copyright information

© Springer-Verlag US 2009

Authors and Affiliations

  • Lucas Brusamarello
    • 1
  • Roberto da Silva
    • 1
  • Gilson I. Wirth
    • 2
  • Ricardo Reis
    • 2
  1. 1.UFRGSUniversidade Federal do Rio Grande do Sul - Instituto de InformáticaPorto AlegreBrazil
  2. 2.UFRGSUniversidade Federal do Rio Grande do Sul - Departamento de Engenharia ElétricaPorto AlegreBrazil

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