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ReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching

  • Marco Paolieri
  • Ivano Bonesana
  • Marco Domenico Santambrogio
Chapter
Part of the IFIP International Federation for Information Processing book series (IFIPAICT, volume 291)

Text pattern matching is one of the main and most computation intensive tasks of applications such as Network Intrusion Detection Systems and DNA Sequencing Matching. Even though software solutions are available, they do not often satisfy the performance requirements, therefore specialized hardware designs can represent the right choice. This paper presents a novel hardware architecture for efficient regular expression matching: ReCPU. This special-purpose processor is able to deal with the common regular expression semantics by treating the regular expressions as a programming language. With the parallelism exploited by the proposed solution a throughput of more than one character comparison per clock cycle (maximum performance of current state of the art solutions) is achieved and just O(n) memory locations (where n is the length of the regular expression) are required. In this paper we are going to expose our complete framework for efficient regular expression matching, both in its architecture and compiler. We present an evaluation of area, time and performance by synthesizing and simulating the configurable VHDL description of the proposed solution. Furthermore, we performed a design space exploration to find the optimal architecture configuration given some initial constraints. We present these results by explaining the idea behind the adopted cost-function.

Keywords

Clock Cycle Pattern Match Regular Expression Finite State Machine Regular Language 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag US 2009

Authors and Affiliations

  1. 1.ALaRIFaculty of Infomatics University of LuganoLuganoSwitzerland
  2. 2.Dipartimento di Elettronica e InformazionePolitecnico di MilanoMilanoItaly

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