Compression-based SoC Test Infrastructures

Part of the IFIP International Federation for Information Processing book series (IFIPAICT, volume 291)

Test Data Compression techniques have been developed for reducing requirements in terms of Automatic Test Equipments. In this paper, we explore the benefits of using these techniques in the context of core-based SoCs. Test Data Compression is used to reduce the system test time by increasing the test parallelism of several cores without the expense of additional tester channels. In this paper, we first discuss the constraints on test architectures and on the design flow inferred by the use of compressed test data. We propose a method for seeking an optimal architecture in terms of total test application time. The method is independent of the compression scheme used for reduction of core test data. The gain in terms of test application time for the SoC is over 50% compared to a test scheme without compression.


Test Time Test Sequence Test Pattern Compression Scheme Test Schedule 
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Copyright information

© Springer-Verlag US 2009

Authors and Affiliations

  1. 1.LIRMMUniv. Montpellier II/CNRSMontpellier cedex 5France

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