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The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm

  • Bassam Mohd
  • Earl E. SwartzlanderJr.
  • Adnan Aziz
Chapter
Part of the IFIP International Federation for Information Processing book series (IFIPAICT, volume 291)

This chapter examines the superscalar pipeline Fast Fourier Transform algorithm and architecture. The algorithm presents a memory management scheme that avoids memory contention throughout the pipeline stages. The fundamental algorithm, a switch-based FFT pipeline architecture and an example 64-point FFT implementation are presented. The pipeline consists of log2N stages, where N is number of FFT points. Each stage can have M Processing Elements (PEs.) As a result, the architecture speed up is M*log2N. The pipeline algorithm is configurable to any M > 1.

Keywords

Pipeline Architecture Switch Fabric Complex Multiplier Swap Operation Twiddle Factor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag US 2009

Authors and Affiliations

  • Bassam Mohd
  • Earl E. SwartzlanderJr.
    • 1
  • Adnan Aziz
  1. 1.ACEThe University of TexasTXAustin

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