A new analytical approach of the impact of jitter on continuous time delta sigma converters.
The performances of continuous time delta sigma converters are severely affected by clock jitter and no generic technique to predict the corresponding degradations is nowadays available. This paper presents a new analytical approach to quantify the power spectral density of jitter errors. This generic computational method can be applied to all kind of continuous time delta sigma converters. Furthermore, clock imperfections are described by means of phase noise spectrum, consequently all possible type of jitters can be taken into account. This paper also describes the temporal non ideal clock models that have been created to simulate the impact of jitter on delta sigma converters and validate the theoretical results.
KeywordsPower Spectral Density Phase Noise Phase Lock Loop Voltage Control Oscillator Loop Filter
- B. E. Boser, B. A. Wooley, “The design of sigma-delta modulation analog-to-digital converters”, IEEE Journal of Solid-State Circuits, vol. 23, December 1988.Google Scholar
- J. A. Cherry, W.M. Snelgrove, “Clock jitter and quantizer metastability in continuous-time delta-sigma modulators”, IEEE Transaction on Circuits and Systems-II, vol. 46, June 1999.Google Scholar
- E. J. Van Der Zwan, E. C. Dijkmans, “A 0.2 mW CMOS ΣΔ modulator for speech coding with 80 dB dynamic range”, IEEE Journal of Solid-State Circuits, vol 31, December 1996.Google Scholar
- M. Ortmanns, F. Gerfers, Y. Manoli, “Fundamental limits of jitter insensitivity in discrete and continuous-time sigma delta modulators”, International Symposium on Circuits and Systems, ISCAS 2003.Google Scholar
- N. Da Dalt, M. Harteneck, C. Sandner, A. Wiesbauer “On the jitter requirements of the sampling clock for analog-to-digital converters”, IEEE Trans. Circuits and Systems-I, vol. 49, September 2002.Google Scholar
- M. Ortmanns, F. Gerfers, Y. Manoli, “A continuous-time ΣΔ modulator with reduced sensitivity to clock jitter through SCR feedback”, IEEE Trans. Circuits and Systems-I, vol 52, May 2005.Google Scholar
- R. Van Veldhoven, “A tri-mode continuous-time ΣΔ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver”, International Solid State Circuits Conference, ISSCC 2003.Google Scholar
- S. Ouzounov et al., “A 1.2V 121-mode CT ΔΣ modulator for wireless receivers in 90nm CMOS”, International Solid State Circuits Conference, ISSCC 2007.Google Scholar
- O. Oliaei, “Continuous-time sigma-delta modulator incorporating semi-digital FIR filters”, International Symposium on Circuits and Systems, ISCAS 2003.Google Scholar
- B. M. Putter, “A ΣΔ ADC with Finite Impulse Response Feedback DAC”, International Solid State Circuits Conference, ISSCC 2004.Google Scholar
- T. C. Weigandt, “Low phase noise, low timing jitter design techniques for delay cell based VCOs and frequency synthesizers”, Ph.D. thesis, University of California, Berkeley, 1998, pp 17–30.Google Scholar