Statistical Blockade: Estimating Rare Event Statistics for Memories

  • Amith Singhee
  • Rob A. Rutenbar
Part of the Integrated Circuits and Systems book series (ICIR)


As we move deeper into sub-65 nm technology nodes, uncontrollable random parametric variations have become a critical hurdle for achieving high yield. This problem is particularly crippling for high-replication circuits (HRCs) – circuits like SRAM cells, nonvolatile memory cells, and other memory cells that are replicated millions of times on the same chip – because of aggressive cell design, the requirement of meeting very high >5σ levels of yield and the usual higher sensitivity of such circuits to process variations. However, it has proved difficult to even estimate such high yield values efficiently, making it very difficult for designers to adopt an accurate, variation-aware design methodology. This chapter develops a general statistical methodology to estimate parametric memory yields. The keystone of the methodology is a technique is called statistical blockade, which combines Monte Carlo simulation, machine learning, and extreme value theory to simulate very rare failure events and to compute analytical models for the tail distributions of the circuit performance metrics. Several circuit examples are analyzed in detail to enable a deep understanding of the theory and its practical use in a real-world setting. The treatment is directed toward both the memory designer and the EDA engineer.


Failure Probability SRAM Cell Extreme Value Theory Faulty Cell Static Noise Margin 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    P. Gupta and F.-L. Heng, Toward a systematic-variation aware timing methodology, Proc. IEEE/ACM Design Automation Conf., June 2004.Google Scholar
  2. 2.
    M. Hane, T. Ikezawa, and T. Ezaki, Atomistic 3d process/device simulation considering gate line-edge roughness and poly-si random crystal orientation effects, Proc. IEEE Int. Electron Devices Meeting, 2003.Google Scholar
  3. 3.
    M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, Matching properties of MOS transistors, IEEE J. Solid-State Circuits, 24(5): 1433–1440, 1989.CrossRefGoogle Scholar
  4. 4.
    A. J. Bhavnagarwala, X. Tang, and J. D. Meindl, The impact of intrinsic device fluctuations on CMOS SRAM cell stability, IEEE J. Solid-State Circuits, 36(4): 658–665, 2001.CrossRefGoogle Scholar
  5. 5.
    S. Mukhopadhyay, H. Mahmoodi, and K. Roy, Statistical design and optimization of SRAM cell for yield enhancement, Proc. IEEE/ACM Int. Conf. on CAD, 2004.Google Scholar
  6. 6.
    B. H. Calhoun and A. Chandrakasan, Analyzing static noise margin for sub-threshold SRAM in 65 nm CMOS, Proc. Eur. Solid State Cir. Conf., 2005.Google Scholar
  7. 7.
    B. Joshi, R. K. Anand, C. Berg, J. Cruz-Rios, A. Krishnamurthi, N. Nettleton, S. Nguyen, J. Reaves, J. Reed, A. Rogers, S. Rusu, C. Tucker, C. Wang, M. Wong, D. Yee, and J.-H. Chang, A BiCMOS 50 MHz cache controller for a superscalar microprocessor, Int. Solid State Cir. Conf., 1992.Google Scholar
  8. 8.
    G. S. Fishman, A First Course in Monte Carlo. Duxbury, 2006.Google Scholar
  9. 9.
    K. Agarwal, F. Liu, C. McDowell, S. Nassif, K. Nowka, M. Palmer, D. Acharyya, and J. Plusquellic, A test structure for characterizing local device mismatches, Symp. on VLSI Circuits Dig. Tech. Papers, 2006.Google Scholar
  10. 10.
    H. Chang, V. Zolotov, S. Narayan, and C. Visweswariah, Parameterized block-based statistical timing analysis with non-Gaussian parameters, nonlinear delay functions, Proc. IEEE/ACM Design Autom. Conf., 2005.Google Scholar
  11. 11.
    T. Ezaki, T. Izekawa, and M. Hane, Investigation of random dopant fluctuation induced device charestistics variation for sub-100 nm CMOS by using atomistic 3D process/device simulator, Proc. IEEE Int. Electron Devices Meeting, 2002.Google Scholar
  12. 12.
    H. Mahmoodi, S. Mukhopadhyay, and K. Roy, Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits, IEEE J. Solid State Cir., 40(3): 1787–1796, 2005.CrossRefGoogle Scholar
  13. 13.
    D. Hocevar, M. Lightner, and T. Trick, A study of variance reduction techniques for estimating circuit yields, IEEE Trans. Computer-Aided Design, 2(3): 279–287, 1983.Google Scholar
  14. 14.
    R. Kanj, R. Joshi, and S. Nassif, Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare event failure, Proc. IEEE/ACM Design Autom. Conf., 2006.Google Scholar
  15. 15.
    T. C. Hesterberg, Advances in Importance Sampling, Dept. of Statistics, Stanford University, 1998, 2003.Google Scholar
  16. 16.
    S. I. Resnick, Extreme Values, Regular Variation and Point Processes, Springer, New York, 1987.MATHGoogle Scholar
  17. 17.
    L. de Haan, Fighting the arch-enemy with mathematics, Statist. Neerlandica, 44: 45–68, 1990.CrossRefMATHMathSciNetGoogle Scholar
  18. 18.
    P. Embrechts, C. Klüppelberg, and T. Mikosch, Modelling Extremal Events for Insurance and Finance, Springer-Verlag, Berlin, 4th ed., 2003.Google Scholar
  19. 19.
    A. Singhee and R. A. Rutenbar, Statistical Blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application, Proc. Design Autom. Test Europe, 2007.Google Scholar
  20. 20.
    A. Singhee, J. Wang, B. H. Calhoun, and R. A. Rutenbar, Recursive Statistical Blockade: an enhanced technique for rare event simulation with application to SRAM circuit design, Proc. Int. Conf. VLSI Design, 2008.Google Scholar
  21. 21.
    R. A. Fisher and L. H. C. Tippett, Limiting forms of the frequency distribution of the largest or smallest member of a sample, Proc. Cambridge Philos. Soc., 24: 180–190, 1928.CrossRefMATHGoogle Scholar
  22. 22.
    B. Gnedenko, Sur la distribution limite du terme maximum d’une aleatoire, Ann. Math., 44(3): 423–453, 1943.CrossRefMathSciNetGoogle Scholar
  23. 23.
    A. Singhee, Novel Algorithms for Fast Statistical Analysis of Scaled Circuits, PhD Thesis, Electrical and Computer Engg., Carnegie Mellon University, 2007.Google Scholar
  24. 24.
    A. A. Balkema and L. de Haan, Residual life time at great age, Ann. Prob., 2(5): 792–804, 1974.CrossRefMATHGoogle Scholar
  25. 25.
    J. Pickands III, Statistical inference using extreme order statistics, Ann. Stats., 3(1): 119–131, 1975.CrossRefMATHGoogle Scholar
  26. 26.
    S. D. Grimshaw, Computing maximum likelihood estimates for the generalized Pareto distribution, Technometrics, 35(2): 185–191, 1993.CrossRefMATHMathSciNetGoogle Scholar
  27. 27.
    R. L. Smith, Estimating tails of probability distributions, Ann. Stats., 15(3): 1174–1207, 1987.CrossRefMATHGoogle Scholar
  28. 28.
    R. L. Smith, Maximum likelihood estimation in a class of non-regular cases, Biometrika, 72: 67–92, 1985.CrossRefMATHMathSciNetGoogle Scholar
  29. 29.
    J. R. M. Hosking and J. R. Wallis, Parameter and quantile estimation for the generalized Pareto distribution, Technometrics, 29(3): 339–349, 1987.CrossRefMATHMathSciNetGoogle Scholar
  30. 30.
    J. R. M. Hosking, The theory of probability weighted moments, IBM Research Report, RC12210, 1986.Google Scholar
  31. 31.
    C. J. C. Burges, A tutorial on support vector machines for pattern recognition, Data Mining and Knowledge Discovery, 2(2): 121–167, 1998.CrossRefGoogle Scholar
  32. 32.
    T. Hastie, R. Tibshirani and J. Friedman, The Elements of Statistical Learning: Data Mining, Inference, and Prediction, Springer, 2001.Google Scholar
  33. 33.
    T. Joachims, Making large-scale SVM learning practical, In B. Schölkopf, C. Burges, and A. Smola, editors, Advances in Kernel Methods – Support Vector Learning. MIT Press, 1999.Google Scholar
  34. 34.
    I. H. Witten and E. Frank, Data Mining: Practical Machine Learning Tools and Techniques, Morgan Kaufmann, San Francisco, 2nd edition, 2005.MATHGoogle Scholar
  35. 35.
    K. Morik, P. Brockhausen, and T. Joachims, Combining statistical learning with a knowledge-based approach – a case study in intensive care monitoring, Proc. 16th Intn’l. Conf. Machine Learning, 1999.Google Scholar
  36. 36.
    R. Rao, A. Srivastava, D. Blaauw, and D. Sylvester, Statistical analysis of subthreshold leakage current for VLSI circuits, IEEE Trans. VLSI Sys., 12(2): 131–139, 2004.CrossRefGoogle Scholar
  37. 37.
    W. Liu, X. Jin, J. Chen, M.-C. Jeng, Z. Liu, Y. Cheng, K. Chen, M. Chan, K. Hui, J. Huang, R. Tu, P. Ko, and C. Hu, BSIM 3v3.2 Mosfet Model Users’ Manual, Univ. California, Berkeley, Tech. Report No. UCB/ERL M98/51, 1988.Google Scholar
  38. 38.
  39. 39.
    R. K. Krishnamurthy, A. Alvandpour, V. de, and S. Borkar, High-performance and low-power challenges for sub-70 nm microprocessor circuits, Proc. Custom Integ. Circ. Conf., 2002.Google Scholar
  40. 40.
    A. Singhee and R. A. Rutenbar, Beyond low-order statistical response surfaces: latent variable regression for efficient, highly nonlinear fitting, Proc. IEEE/ACM Design Autom. Conf., 2007.Google Scholar
  41. 41.
    L. Chang, D. M. Fried, J. Hergenrother, J. W. Sleight, R. H. Dennard, R. K. Montoye, L. Sekaric, S. J. McNab, A. W. Topol, C. D. Adams, K. W. Guarini, and W. Haensch, Stable SRAM Cell Design for the 32 nm Node and Beyond, Symp. VLSI Tech. Dig. Tech. Papers, 128–129, 2005.Google Scholar
  42. 42.
    J. Wang, A. Singhee, R. A. Rutenbar, and B. H. Calhoun, Modeling the minimum standby supply voltage of a full SRAM array, Proc. Europ. Solid State Cir. Conf., 2007.Google Scholar
  43. 43.
    W. H. Press, B. P. Flannery, A. A. Teukolsky, and W. T. Vetterling, Numerical Recipes in C: The Art of Scientific Computing, Cambridge University Press, 2nd edition, 1992.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  • Amith Singhee
  • Rob A. Rutenbar
    • 1
  1. 1.Electrical and Computer EngineeringCarnegie Mellon UniversityPittsburghUSA

Personalised recommendations