Embedded Magnetic RAM

  • Hideto Hidaka
Part of the Integrated Circuits and Systems book series (ICIR)


In Chapter 7, magnetic RAM (MRAM) technology is introduced as a key technology candidate for creating new applications such as nonvolatile RAM. After an introduction of the history and basic principles of MRAM, we look into MRAM technology and basic design as well as on various memory cell architectures in Section 7.1. Then overviews on representative MRAM design examples, possible applications, and future challenges of MRAM are provided in Section 7.2. Finally nonvolatile memory frontiers and challenges are discussed in Section 7.3 as a conclusion of Chapters 6 and 7. The focus of this chapter is to highlight and summarize important concepts of the new technology.


Hard Disk Drive Flash Memory Ferromagnetic Layer Current Driver Magnetic Tunneling Junction 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



The author of Chapters 6 and 7 thanks all the members in the Flash-MCU Development Department, Renesas Technology Corp. for their help in providing the data, technical details, and fruitful discussions. These chapters are dedicated to C. H. and late F. A.


  1. 1.
    Andre T W, Nahas J J, Subramanian C K, Garni B J, Lin H S, Omair A, Martino W L (2005) A 4-Mb 0.18-μ/m 1T1MTJ toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers. IEEE J. Solid-State Circuits 40 1: 301–309CrossRefGoogle Scholar
  2. 2.
    DeBrosse J, Arndt C, Barwin C, Bette A, Gogl D, Gow E, Hoenigschmid H, Lammers S, Lamorey M, Lu Y, Maffitt T, Maloney K, Obermeyer W, Sturm A, Viehmann H, Willmott D, Wood M, Gallagher W J, Mueller G, Sitaram A R (2004) A 16 Mb MRAM featuring bootstrapped write drivers. Symp. VLSI Circuits, Dig. Tech. Papers :454–457Google Scholar
  3. 3.
    Durlam M, Naji P, DeHerrera M, Tehrani S, Kerszykowski G, Kyler K (2000) Nonvolatile RAM based on Magnetic Tunnel Junction Elements. Dig Tech Papers ISSCC: 130–131Google Scholar
  4. 4.
    Freedman T L (2005) The World is Flat: A brief history of the twenty-first century. FSGGoogle Scholar
  5. 5.
    Gogl D, Arndt C, Barwin J C, Bette A, DeBrosse J, Gow E, Hoenigschmid H, Lammers S, Lamorey M, Lu Y, Maffitt T, Maloney K, Obermaier W, Sturm A, Viehmann H, Willmott D, Wood M, Gallagher W J, Mueller G, Sitaram A R (2005) A 16-Mb MRAM Featuring Bootstrapped Write Drivers. IEEE J Solid-State Circuits 40 4: 902–908CrossRefGoogle Scholar
  6. 6.
    Hidaka H (2006) Embedded Memory Challenges for Innovations. Proc. Syst. LSI Workshop, IEICE Japan, Nov.27Google Scholar
  7. 7.
    Hidaka H (2007) Embedded NV memory design. ISSCC2007 NV-Memory Forum, Feb. 11Google Scholar
  8. 8.
    Hosomi M, Yamagishi H, Yamamoto T, Bessho K, Higo Y, Yamane K, Yamada H, Shoji M, Hachino H, Fukumoto C, Nagao H, and Kano H (2005) A Novel Nonvolatile Memory with Spin Torque Transfer Magnetization Switching: Spin-RAM. IEDM Tech. Dig. 459–462Google Scholar
  9. 9.
    Iwata Y, Tsuchida K, Inaba T, Shimizu Y, Takizawa R, Ueda Y, Sugibayashi T, Asao Y, Kajiyama T, Hosotani K, Ikegawa S, Kai T, Nakayama M, Tahara S and Yoda H (2006) A 16 Mb MRAM with FORK Wiring Scheme and Burst Modes. Dig. Tech. Papers ISSCC: 477–486Google Scholar
  10. 10.
    Julliere M (1975) Tunneling between ferromagnetic films. Phys. Lett. 54A : 225–226Google Scholar
  11. 11.
    Katti R R (2003) Giant Magnetoresistive Random-Access Memories Based on Current-in-Plane Devices. Proc. IEEE 91 5: 687–702.Google Scholar
  12. 12.
    Kawahara T, Takemura R, Miura K, Hayakawa J, Ikeda S, Lee Y M, Sasaki R, Goto Y, Ito K, Meguro T, Matsukura F, Takahashi H, Matsuoka H, Ohno H (2007) 2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read. Dig. Tech. Papers ISSCC :480–481Google Scholar
  13. 13.
    Kim W C and Mauborgne R (2005) Blue Ocean Strategy. HBS Press :16–17Google Scholar
  14. 14.
    Nahas J, Andre T, Subramanian C, Garni B, Lin H, Omair A, and Martino W (2004) A 4 Mb 0.18  μm 1T1MTJ toggle MRAM memory. Dig. Tech. Papers ISSCC: 44–45Google Scholar
  15. 15.
    Nahas J J, Andre T, Subramanian C, Lin H, Alam S M, Papworth K, and Martino W (2007) A 180 Kbit Embeddable MRAM Memory Module. Custom Integrated Circuits Conference:791–794Google Scholar
  16. 16.
    Ohnigian S, Weilerstein I M, Murray D E, and Solomon J (1966) Design of Integrated Selection and Recirculation Circuitry for a High-speed, Low-Power, Magnetic Thin-Film Memory. Dig. Tech. Papers ISSCC:102–103Google Scholar
  17. 17.
    Sakimura N, Sugibayashi T, Honda T, Miura S, Numata H, Hada H, and Tahara S (2003) A 512 Kb Cross- Point Cell MRAM. Dig. Tech. Papers ISSCC:278–279Google Scholar
  18. 18.
    Sakimura N, Sugibayashi T, Honda T, Honjo H, Saito S, Suzuki T, Ishiwata N, and Tahara S (2007) MRAM Cell Technology for Over 500-MHz SoC. IEEE J. Solid-State Circuits 42 4: 830–838CrossRefGoogle Scholar
  19. 19.
    Sakimura N, Sugibayashi T, Nebashi R, Honjo H, Saito S, Kato Y, and Kasai N (2007) A 250-MHz 1-Mbit Embedded MRAM Macro Using 2T1MTJ Cell with Bitline Separation and Half-Pitch Shift Architecture. IEEE Asian Solid-State Circuits Conference: 216–219Google Scholar
  20. 20.
    Scheuerlein R, Gallagher W, Parkin S, Lee A, Ray S, Robertazzi R, and Reohr W (2000) A 10 ns read and write non-volatile memory array using a magnetic tunnel junction and FET switch in each cell. Dig. Tech. Papers ISSCC: 128–129Google Scholar
  21. 21.
    Slonczewski J C (1989) Conductance and exchange coupling of two ferromagnets separated by a tunneling barrier. Phys Rev B Volume 39, Number 10: 6995–7002CrossRefGoogle Scholar
  22. 22.
    Tanizaki H, Tsuji T, Otani J, Yamaguchi Y, Murai Y, Furuta H, Ueno S, Oishi T, Hayashikoshi M, and Hidaka H (2006) A high-density and high-speed 1T-4MTJ MRAM with Voltage Offset Self-Reference Sensing Scheme. Proc. Tech. Papers Asian Solid-State Circuits Conference: 303–306Google Scholar
  23. 23.
    Tsuji T, Tanizaki H, Ishikawa M, Otani J, Yamaguchi Y, Ueno S, Oishi T, and Hidaka H (2004) A 1.2 V 1 Mbit embedded MRAM core with folded bit-line array architecture. Dig. Tech. Papers, Symp. VLSI Circuits :450–453Google Scholar
  24. 24.
    Ueno S, Eimori T, Kuroiwa T, Furuta H, Tsuchimoto J, Maejima S, Iida S, Ohshita H, Hasegawa S, Hirano S, Yamaguchi T, Kurisu H, Yutani A, Hashikawa N, Maeda H, Ogawa Y, Kawabata K, Okumura Y, Tsuji T, Ohtani J, Tanizaki T, Yamaguchi Y, Ohishi T, Hidaka H, Takenaga T, Beysen S, Kobayashi H, Oomori T, Koga T, Ohji Y (2004) A 0.13  μm MRAM with 0.26 × 0.44  μm2 MTJ optimized on universal MR-RA relation for 1.2 V high-speed operation beyond 143 MHz. Tech. Dig. Int. Electron Device Meeting:579–582Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  • Hideto Hidaka
    • 1
  1. 1.MCU Technology Division, Renesas Technology CorporationTokyoJapan

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