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Embedded Memories for Nano-Scale VLSIs pp 89–126Cite as

Ultra Low Voltage SRAM Design

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Part of the book series: Integrated Circuits and Systems ((ICIR))

Abstract

Aggressive scaling of the supply voltage to SRAMs greatly minimizes their active and leakage power, a dominating portion of the total power in an increasing number of applications. Hence, highly energy-constrained systems, where performance requirements are secondary, benefit greatly from SRAMs that provide read and write functionality at the lowest possible voltage, particularly down to 0.3 V. However, conventional bit-cells and architectures, designed to operate at nominal supply voltages, come far short of achieving the voltage scalability required. This chapter investigates the basic degradation mechanisms in the underlying MOSFET devices, and the resulting failures modes plaguing low-voltage SRAMs. Specific solutions to manage all of these are analyzed with respect to the associated density, performance, and power trade-offs. Actual design examples are cited that achieve full read and write functionality down to 0.3 V, where the leakage-power savings can exceed a factor of 50 compared to nominal supplies.

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  1. Massachusetts Institute of Technology, Cambridge, MA, USA

    Naveen Verma & Anantha P. Chandrakasan

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  1. Naveen Verma
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  2. Anantha P. Chandrakasan
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    Verma, N., Chandrakasan, A.P. (2009). Ultra Low Voltage SRAM Design. In: Zhang, K. (eds) Embedded Memories for Nano-Scale VLSIs. Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-88497-4_4

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    • DOI: https://doi.org/10.1007/978-0-387-88497-4_4

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