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Ultra Low Voltage SRAM Design

  • Naveen Verma
  • Anantha P. Chandrakasan
Chapter
Part of the Integrated Circuits and Systems book series (ICIR)

Abstract

Aggressive scaling of the supply voltage to SRAMs greatly minimizes their active and leakage power, a dominating portion of the total power in an increasing number of applications. Hence, highly energy-constrained systems, where performance requirements are secondary, benefit greatly from SRAMs that provide read and write functionality at the lowest possible voltage, particularly down to 0.3 V. However, conventional bit-cells and architectures, designed to operate at nominal supply voltages, come far short of achieving the voltage scalability required. This chapter investigates the basic degradation mechanisms in the underlying MOSFET devices, and the resulting failures modes plaguing low-voltage SRAMs. Specific solutions to manage all of these are analyzed with respect to the associated density, performance, and power trade-offs. Actual design examples are cited that achieve full read and write functionality down to 0.3 V, where the leakage-power savings can exceed a factor of 50 compared to nominal supplies.

Keywords

Supply Voltage Access Device Soft Error Driver Device Leakage Power 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    M. Agostinelli, J. Hicks, J. Xu, B. Woolery, K. Mistry, K. Zhang, S. Jacobs, J. Jopling, W. Yang, B. Lee, T. Raz, M. Mehalel, P. Kolar, Y. W. J. Sandford, D. Pivin, C. Peterson, M. DiBattista, S. Pae, M. Jones, S. Johnson, and G. Subramanian, “Erratic fluctuations of SRAM cache Vmin at the 90 nm process technology node,” in IEDM Dig. Tech. Papers, Dec. 2005, pp. 671–674.Google Scholar
  2. 2.
    A. Bhavnagarwala, X. Tang, and J. Meindl, “The impact of intrinsic device fluctuations on CMOS SRAM cell stability,” IEEE Journal of Solid-State Circuits, vol. 36, no. 4, April 2001, pp. 658–665.CrossRefGoogle Scholar
  3. 3.
    B. Calhoun and A. Chandrakasan, “Ultra-dynamic voltage scaling using sub-threshold operation and local voltage dithering in 90 nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2005, pp. 300–301.Google Scholar
  4. 4.
    B. Calhoun and A. Chandrakasan, “A 256 kb sub-threshold SRAM in 65 nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2006, pp. 480–481.Google Scholar
  5. 5.
    B. H. Calhoun, A. Wang, and A. Chandrakasan, “Modeling and sizing for minimum energy operation in subthreshold circuits,” IEEE Journal of Solid-State Circuits, vol. 40, no. 5, Sept. 2005, pp. 1778–1786.CrossRefGoogle Scholar
  6. 6.
    A. P. Chandrakasan and R. Brodersen, “Minimizing power consumption in digital CMOS circuits,” in Proc. IEEE, vol. 83, no. 4, April 1995, pp. 498–523.CrossRefGoogle Scholar
  7. 7.
    I. J. Chang, J.-J. Kim, S. P. Park, and K. Roy, “A 32 kb 10T subthreshold SRAM array with bit-interleaving and differential read-scheme in 90 nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2008, pp. 388–389.Google Scholar
  8. 8.
    L. Chang, D. M. Fried, J. Hergenrother, J. W. Sleight, R. H. Dennard, R. Montoye, L. Sekaric, S. J. McNab, A. W. Topol, C. D. Adams, K. W. Guarini, and W. Haensch, “Stable SRAM cell design for the 32 nm node and beyond,” in Proc. IEEE Symp. VLSI Circuits, June 2005, pp. 128–129.Google Scholar
  9. 9.
    L. Chang, Y. Nakamura, R. Montoye, J. Sawada, A. K. Martin, K. Kinoshita, F. H. Gebara, K. B. Agarwal, D. J. Acharyya, W. Haensch, K. Hosokawa, and D. Jamsek, “A 5.3 GHz 8T-SRAM with operation down to 0.41 V in 65 nm CMOS,” in Proc. IEEE Symp. VLSI Circuits, June 2007, pp. 252–253.Google Scholar
  10. 10.
    J. Chen, L. Clark, and T.-H. Chen, “An ultra-low-power memory with a sub-threshold power supply voltage,” IEEE Journal of Solid-State Circuits, vol. 41, no. 10, Oct. 2006, pp. 2344–2353.CrossRefGoogle Scholar
  11. 11.
    F. Jumel, P. Royannez, H. Mair, D. Scott, A. Er Rachidi, R. Lagerquist, M. Chau, S. Gururajarao, S. Thiruvengadam, M. Clinton, V. Menezes, R. Hollingsworth, J. Vaccani, F. Piacibello, N. Culp, J. Rosal, M. Ball, F. Ben-Amar, L. Bouetel, O. Domerego, J. L. Lachese, C. Fournet-Fayard, J. Ciroux, C. Raibaut, U. Ko, “A leakage management system based on clock gating infrastructure for a 65-nm digital base-band modem chip,” in Proc. IEEE Symp. VLSI Circuits, June 2006, pp. 214–215.Google Scholar
  12. 12.
    A. Kawasumi, T. Yabe, Y. Takeyama, O. Hirabayashi, K. Kushida, A. Tohata, T. Sasaki, A. Katayama, G. Fukano, Y. Fujimura, N. Otsuka, “A single-power-supply 0.7 V 1 GHz 45 nm SRAM with an asymmetrical unit-β-ratio memory cell,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2008, pp. 382–383.Google Scholar
  13. 13.
    M. Khare, S. H. Ku, R. A. Donaton, S. Greco, C. Brodsky, X. Chen, A. Chou, R. DellaGuardia, S. Deshpande, B. Doris, S. K. H. Fung, A. Gabor, M. Gribelyuk, S. Holmes, F. F. Jamin, W. L. Lai, W. H. Lee, Y. Li, P. McFarland, R. Mo, S. Mittl, S. Narasimha, D. Nielsen, R. Purtell, W. Rausch, S. Sankaran, J. Snare, L. Tsou, A. Vayshenker, T. Wagner, D. Wehella-Gamage, E. Wu, S. Wu, W. Yan, E. Barth, R. Ferguson, P. Gilbert, D. Schepis, A. Sekiguchi, R. Goldblatt, J. Welser, K. P. Muller, P. Agnello, “A high performance 90 nm SOI technology with 0.992 μm2 6T-SRAM cell,” in IEEE IEDM Dig. Tech. Papers, Dec. 2002, pp. 8–11.Google Scholar
  14. 14.
    T.-H. Kim, J. Liu, J. Kean, and C. H. Kim, “A high-density subthreshold SRAM with data-independent bitline leakage and virtual ground replica scheme,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2007, pp. 330–331.Google Scholar
  15. 15.
    T.-H. Kim, J. Liu, J. Kean, and C. H. Kim, “A 0.2 V, 480 kb subthreshold SRAM with 1 k cells per bitline for ultra-low –voltage computing,” IEEE Journal of Solid-State Circuits, vol. 43, no. 2, Feb. 2008, pp. 518–529.CrossRefGoogle Scholar
  16. 16.
    J. P. Kulkarni, K. Kim, and K. Roy, “A 160 mV robust schmitt trigger based subthreshold SRAM,” IEEE Journal of Solid-State Circuits, vol. 42, no. 10, Oct. 2007, pp. 2303–2313.CrossRefGoogle Scholar
  17. 17.
    J. Kwong, Y. Ramadass, N. Verma, M. Koesler, K. Huber, H. Moormann, and A. Chandrakasan, “A 65 nm Sub-Vt Microcontroller with Integrated SRAM and Switch Capacitor DC-DC Converter,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 318–319.Google Scholar
  18. 18.
    Z. Liu and V. Kursun, “High read stability and low leakage SRAM cell based on data/bitline decoupling,” in Proc. IEEE Int. Syst Chip Conf.,Sept. 2006, pp. 115–116.Google Scholar
  19. 19.
    C.-Y. Lu and J. M. Sung, “Reverse short-channel effect on threshold voltage of submicrometer salicide devices,” IEEE Electron Device Letters, vol. 10, no. 10, Oct. 1989, pp. 446–448.CrossRefGoogle Scholar
  20. 20.
    T. Mizumo, J.-I. Okamura, and A. Toriumi, “Experimental study of threshold voltage fluctuations using an 8 k MOSFET’s array,” in Proc. IEEE Symp. VLSI Tech., May 1993, pp. 41–42.Google Scholar
  21. 21.
    Y. Morita, H. Fujiwara, H. Noguchi, Y. Iguchi and H. Kawaguchi, and M. Yoshimoto, “An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design Under DVS Environment,” in Symp. VLSI Circuits, June 2007, pp. 256–257.Google Scholar
  22. 22.
    S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, “1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS,” IEEE Journal of Solid-State Circuits, vol. 30, no. 8, Aug. 1995, pp. 847–854.CrossRefGoogle Scholar
  23. 23.
    M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching properties of MOS transistors,” IEEE Journal of Solid-State Circuits, vol. 24, no. 5, Oct. 1989, pp. 1433–1439.CrossRefGoogle Scholar
  24. 24.
    R. Rodriguez, J. H. Stathis, B. P. Linder, S. Kowalczyk, C. T. Chuang, R. V. Joshi, G. Northrop, K. Bernstein, A. J. Bhavnagarwala, and S. Lombardo, “The impact of gate-oxide breakdown on SRAM stability,” IEEE Electron Device Letters, vol. 23, no. 9, Sept. 2002, pp. 559–561.CrossRefGoogle Scholar
  25. 25.
    E. Seevinck, F. J. List, and J. Lohstroh, “Static-noise margin analysis of MOS SRAM cells,” IEEE Journal of Solid-State Circuits, vol. SC-22, no. 5, Oct. 1987, pp. 748–754.CrossRefGoogle Scholar
  26. 26.
    S.-W. Sun and P. G. Y. Tsui, “Limitations of CMOS supply-voltage scaling by MOSFET threshold-voltage variation,” IEEE Journal of Solid-State Circuits, vol. 30, no. 8, Aug. 1995, pp. 947–949.CrossRefGoogle Scholar
  27. 27.
    R. M. Swanson and J. D. Meindl, “Ion-implanted complementary MOS transistor in low-voltage circuits,” IEEE Journal of Solid-State Circuits, vol. sc-7, no. 2, Apr. 1972, pp. 146–153.CrossRefGoogle Scholar
  28. 28.
    V. Sze, R. Blazquez, M. Bhardwaj, and A. Chandrakasan, “An energy efficient subthreshold baseband processor architecture for pulsed ultra-wideband communications,” in IEEE Int. Conf Acoust., Speech and Signal Process., May 2006, pp. 908–911.Google Scholar
  29. 29.
    K. Takeda, Y. Hagihara, Y. Aimoto, M. Nomura, Y. Nakazawa, T. Ishii, and H. Kobatake, “A read-static-noise-margin-free SRAM cell for low-VDDand high-speed applications,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2005, pp. 478–479.Google Scholar
  30. 30.
    N. Verma and A. Chandrakasan, “A 256 kb 65 nm 8T sub-VtSRAM employing sense-amplifier redundancy,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2007, pp. 328–329.Google Scholar
  31. 31.
    N. Verma, and A. P. Chandrakasan, “A 256 kb 65 nm 8T subthreshold SRAM employing Sense-amplifier Redundancy,” IEEE Journal of Solid-State Circuits, vol. 43, no. 1, Jan. 2008, pp. 141–149.CrossRefGoogle Scholar
  32. 32.
    N. Verma and A. P. Chandrakasan, “A high-density 45 nm SRAM using small-signal non-strobed regenerative sensing,” ISSCC Digest of Technical Papers, Feb. 2008, pp. 380–381.Google Scholar
  33. 33.
    N. Verma, J. Kwong, and A. P. Chandrakasan, “Nanometer MOSFET variation in minimum energy subthreshold circuits,” IEEE Transaction Electron Devices, vol. 55, no. 1, Jan. 2008, pp. 163–174.CrossRefGoogle Scholar
  34. 34.
    J. Wang and B. H. Calhoun, “Canary replica feedback for near-DRV stand-by VDD scaling in a 90 nm SRAM,” in Proc. IEEECustom Integr. Circuits Conf.,Sept. 2007, pp. 29–32.Google Scholar
  35. 35.
    Y. Wang, H. Ahn, U. Bhattacharya, et al., “A 1.1 GHz 12AμA/Mb-leakage SRAM design in 65 nm ultra-low-power CMOS with integrated leakage reduction for mobile applications,” ISSCC Digest of Technical Papers, Feb. 2007, pp. 324–325.Google Scholar
  36. 36.
    A. Wang, A. Chandrakasan, and S. Kosonocky, “ Optimal supply and threshold scaling for sub-threshold CMOS circuits,” in Proc. IEEE Comp Soc. Annu. Symp. VLSI, April 2002, pp. 5–9.Google Scholar
  37. 37.
    A. Wang and A. Chandrakasan, “A 180 mV FFT processor using sub-threshold circuit techniques,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2004, pp. 292–293.Google Scholar
  38. 38.
    Y. Ye, S. Borkar, and V. De, “A new technique for standby leakage reduction in high performance circuits,” in Proc. IEEE Symp. VLSI Circuits, June 1998, pp. 40–41.Google Scholar
  39. 39.
    K. Zhang, K. Hose, V. De, and B. Senyk, “The scaling of data sensing schemes for high speed cache design in sub-0.18μm technologies,” in Proc. IEEE Symp. VLSI Circuits, June 2000, pp. 226–227.Google Scholar
  40. 40.
    K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepath, Y. Wang, B. Zheng, M. Bohr, “A 3-GHz 70 Mb SRAM in 65 nm CMOS technology with integrated column-based dynamic power supply,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2005, pp. 474–475.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  • Naveen Verma
    • 1
  • Anantha P. Chandrakasan
    • 1
  1. 1.Massachusetts Institute of TechnologyCambridgeUSA

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