Embedded SRAM Design in Nanometer-Scale Technologies

  • Hiroyuki Yamauchi
Part of the Integrated Circuits and Systems book series (ICIR)


Static random access memory (SRAM) has been embedded in almost all of VLSI chips and has played a key role in the wide variety of applications required to enhance the performances of high speed, high density, low power, low voltage, low cost, time to market. Embedded SRAM has had a long reign in upper memory hierarchy than any other memories such as dynamic random access memory (DRAM). This is largely because SRAM is able to provide the highest random access speed performance among various embedded memory technologies. In addition, SRAM is fully compatible with CMOS logic process technology and operating voltage, enabling a seamless integration with logic circuits. Meanwhile, the device miniaturization driven by the technology scaling into nanometer regime has made it more challenging to maintain a sufficient SRAM cell stability margin while continuing to increase a random access speed as the transistor threshold voltage mismatching becomes significant. This also makes it more difficult to scale the operating voltage (V DD) while keeping the compatibility with logic’s. This chapter intends to provide an overview on the state-of-the-art SRAM circuit design technologies to address the key SRAM challenges in nanometer-scale technologies in terms of the read/write stability margins, cell current, and leakages.


Cell Current Storage Node Read Operation Dynamic Random Access Memory Static Random Access Memory 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  1. 1.Fukuoka Institute of TechnologyFukuokaJapan

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