Embedded SRAM Design in Nanometer-Scale Technologies

Part of the Integrated Circuits and Systems book series (ICIR)


Static random access memory (SRAM) has been embedded in almost all of VLSI chips and has played a key role in the wide variety of applications required to enhance the performances of high speed, high density, low power, low voltage, low cost, time to market. Embedded SRAM has had a long reign in upper memory hierarchy than any other memories such as dynamic random access memory (DRAM). This is largely because SRAM is able to provide the highest random access speed performance among various embedded memory technologies. In addition, SRAM is fully compatible with CMOS logic process technology and operating voltage, enabling a seamless integration with logic circuits. Meanwhile, the device miniaturization driven by the technology scaling into nanometer regime has made it more challenging to maintain a sufficient SRAM cell stability margin while continuing to increase a random access speed as the transistor threshold voltage mismatching becomes significant. This also makes it more difficult to scale the operating voltage (V DD) while keeping the compatibility with logic’s. This chapter intends to provide an overview on the state-of-the-art SRAM circuit design technologies to address the key SRAM challenges in nanometer-scale technologies in terms of the read/write stability margins, cell current, and leakages.


Cell Current Storage Node Read Operation Dynamic Random Access Memory Static Random Access Memory 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    I. Chang, J-J. Kim, S. Park, K. Roy, West Lafayette, 21.7 “A 32 kb 10 T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90 nm CMOS” IEEE Solid States Circuits Conference 2008Google Scholar
  2. 2.
    L. Chang, D. M. Fried, J. Hergenrother, J. W. Sleight, R. H. Dennard, R. K. Montoye, L. Sekaric, S. J. McNab, A. W. Topol, C. D. Adams, K. W. Guarini, and W. Haensch, “Stable SRAM Cell Design for the 32 nm Node and Beyond” IEEE 2005 Symposium on VLSI TechnologyGoogle Scholar
  3. 3.
    L. Chang, Y. Nakamura, R. K. Montoye, J. Sawada, A. K. Martin, K. Kinoshita, F. H. Gebara, K. B. Agarwal, D. J. Acharyya, W. Haensch, K. Hosokawa, and D. Jamsek, “A 5.3 GHz 8T-SRAM with Operation Down to 0.3.1 V in 65 nm CMOS”, IEEE 2007 Symposium on VLSI CircuitsGoogle Scholar
  4. 4.
    Y. H. Chen, W. M. Chan, S. Y. Chou, H. J. Liao, H. Y. Pan, J. J. Wu, C. H. Lee, S. M. Yang, Y. C. Liu, H. Yamauchi, “A 0.6 V 45 nm Adaptive Dual-rail SRAM Compiler Circuit Design for Lower VDD_ min VLSIs 21.3” IEEE 2008 Symposium on VLSI CircuitsGoogle Scholar
  5. 5.
    Y. Chung and S.-W. Shim, “An Experimental 0.8 V 256-kbit SRAM Macro with Boosted Cell Array Scheme”, ETRI Journal, Volume 29, Number 4, 2007Google Scholar
  6. 6.
    H. F. Hamzaoglu, K. Zhang, Y. Wang, H.-J. Ahn, U. Bhattacharya, Z. Chen, Y.-G. Ng, A. Pavlov, K. Smits*, M. Bohr, 21.1, “A 153 Mb SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45 nm Hi-K Metal Gate CMOS Technology” IEEE Solid States Circuits Conference 2008Google Scholar
  7. 7.
    K. Ishibashi, K.-I. Takasugi, T. Yamanaka, Member, T. Hashimoto, and K. Sasaki, “A 1-V TFT-Load SRAM Using a Two-step Word-Voltage Method”, IEEE Journal of Solid-state Circuits. Volume 21, Number 2 1992Google Scholar
  8. 8.
    K. Itoh, M. Horiguchi, M. Yamaoka, “Low-Voltage Limitations of Memory-Rich Nano-Scale CMOS LSIs” 33rd European Solid State Circuits Conference, 2007. ESSCIRC 11–13 Sept. 2007 pp. 68–75Google Scholar
  9. 9.
    A. Kawasumi, N. Otsuka, T. Yabe, Y. Takeyama, O. Hirabayashi, K. Kushida, A. Tohata, T. Sasaki, A. Katayama, G. Fukano, Y. Fujimura, 21.4 “A Single-Power-Supply 0.7 V 1 GHz 45 nm SRAM with a Asymmetrical Unit-β-Ratio Memory Cell” IEEE Solid States Circuits Conference 2008Google Scholar
  10. 10.
    M. Khellah et al. “Wordline & Bitline Pulsing Schemes for Improving SRAM Cell Stability in Low-Vcc 65 nm CMOS Designs”, IEEE Symposium on VLSI Circuits 2006Google Scholar
  11. 11.
    K. J. Kuhn, “Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS” pp. 471–474, IEEE IEDM 2007Google Scholar
  12. 12.
    H. Mair, A. Wang, G. Gammie, D. Scott, P. Royannez, S. Gururajarao, M. Chau, R. Lagerquist, L. Ho, M. Basude, N. Culp, A. Sadate, D. Wilson, F. Dahan, J. Song, B. Carlson, U. Ko, “A 65 nm Mobile Multimedia Applications Processor with an Adaptive Power Management Scheme to Compensate for Variations”, IEEE 2007 Symposium on VLSI CircuitsGoogle Scholar
  13. 13.
    Y. Morita, H. Fujiwara, H. Noguchi, Y. Iguchi, K. Nii, H. Kawaguchi, and M. Yoshimoto, “An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment” 2007 Symposium on VLSI CircuitsGoogle Scholar
  14. 14.
    S.Ohbayashi, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda, M. Igarashi, M. Takeuchi, H. Kawashima, H. Makino, Y. Yamaguchi, K. Tsukamoto, M. Inuishi, K. Ishibashi, H. Shinohara, “A 65 nm Soc Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits”, IEEE 2006 Symposium on VLSI CircuitsGoogle Scholar
  15. 15.
    K. Osada, Y. Saitoh, E. Ibe, K. Ishibashi, “16.7fF/Cell Tunnel-Leakage-Suppressed 16-Mb SRAM for Handing Consmic-Ray-Induced Multi-errors”, IEEE Solid-States-Circuits Conference, Vol. 1 pp. 302–494, 2003Google Scholar
  16. 16.
    H. Pilo, J. Barwin, G. Braceras, C. Browning, S. Burns, J. Gabric, S. Lamphier, M. Miller, A. Roberts, F. Towler, “An SRAM Design in 65 nm and 45 nm Technology Nodes Featuring Read and Write-Assist Circuits to Expand Operating Voltage”, IEEE 2006 Symposium on VLSI CircuitsGoogle Scholar
  17. 17.
    H. Pilo, V. Ramadurai, G. Braceras, J. Gabric, S. Lamphier, Y. Tan, “A 450 ps Access-Time SRAM Macro in 45 nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management” 21.7, IEEE Solid States Circuits Conference 2008Google Scholar
  18. 18.
    N. Shibata, et al., “A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment – sure write operation by using step-down negatively overdriven bitline scheme”, IEEE Journal of Solid-State-Circuits, Volume 3.1, Number 3, pp.728–73.2. 2006CrossRefGoogle Scholar
  19. 19.
    T. Suzuki, H. Yamauchi et al., “A Stable SRAM Cell Design Against Simultaneously R/W Disturbed Accesses”, IEEE Symposium on VLSI Circuits, 2.2, 2006Google Scholar
  20. 20.
    Y. Tsukamoto et al., 5A.2 “Worst-Case Analysis to Obtain Stable Read/Write DC Margin of High Density 6T-SRAM-Array with Local Vth Variability”, International Conference on Computer-Aided Design, 2005Google Scholar
  21. 21.
    D.-P. Wang, H.-J. Liao, H. Yamauchi, W. Hwang, Y. L. Lin, Y. H. Chen, H. C. Chang, “A 45 nm Dual-Port SRAM with Write and Read Capability Enhancement at Low Voltage”, IEEE SOCC 2007Google Scholar
  22. 22.
    M. Yabuuchi, K. Nii, Y. Tsukamoto, et al., “A 45 nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations”, Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International, pp. 326–606, 11–15 Feb. 2007 Google Scholar
  23. 23.
    M. Yamaoka, N. Maeda, Y. Shimazaki, K. Osada, 21.5 “A 65 nm Low-Power High-Density SRAM Operable at 1.0 V Under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS” IEEE Solid States Circuits Conference 2008Google Scholar
  24. 24.
    M. Yamaoka, K. Osada, R. Tsuchiya, M. Horiuchi, S. Kimura, T. Kawahara, “Low Power SRAM Menu for SoC Application using Yin-Yang-Feedback Memory Cell Technology”, 2004 Symposium on VLSI CircuitsGoogle Scholar
  25. 25.
    H. Yamauchi, USP 5680356, Oct. 21, 1997Google Scholar
  26. 26.
    H. Yamauchi, USP 6898111, May.23.2005Google Scholar
  27. 27.
    H. Yamauchi “Embedded SRAM Design”, tutorial in IEEE ASSCC 2006Google Scholar
  28. 28.
    H. Yamauchi “Embedded SRAM Circuit Design Technologies for a 45 nm and Beyond” (Invited Paper) 5.2-I, The 7th International Conference on ASIC (ASICON) 2007, Oct. 2007Google Scholar
  29. 29.
    H. Yamauchi, “Embedded SRAM Trend in Nano-Scale CMOS” (Invited Paper), IEEE International Workshop on Memory Technology, Design, and Testing (MTDT), Dec. 2007Google Scholar
  30. 30.
    H. Yamauchi, “Embedded SRAM Design and Trend” IEEE ISSCC 2008, Memory forum “Embedded Memory Design for Nano-scale VLSI system”, 2008Google Scholar
  31. 31.
    H. Yamauchi et al., “A Circuit Design to Suppress Asymmetrical Characteristics in High-Density DRAM Sense Amplifiers”, IEEE Journal of Solid-State Circuits, Volume 25, 1990Google Scholar
  32. 32.
    H. Yamauchi, et al., “A 0.8 V/100 MHz/sub-5 mW-operated mega-bit SRAM cell architecture with charge-recycle offset-source driving (OSD) scheme” IEEE Symposium on VLSI Circuits 1996, 126–127, June, 1996Google Scholar
  33. 33.
    H. Yamauchi et al., “A 0.5 V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes”, IEEE Low Power Electronics and design., pp.49–54, 1996Google Scholar
  34. 34.
    H. Yamauchi et al., “Gate-over-driving CMOS architecture for 0.5 V single-power-supply-operated devices”, IEEE Solid States Circuits Conference, pp.290–291, 1997Google Scholar
  35. 35.
    H. Yamauchi et al., “A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture“, IEEE Transaction on Very Large Scale Integration (VLSI) Systems Volume 5, Number 4, pp. 377–387, 1997Google Scholar
  36. 36.
    H. Yamauchi et al., “A Differential Cell Terminal Biasing Scheme Enabling A Stable Write Operation Against A Large Random Threshold Voltage (Vth) Variation”, IEICE EC , Volume 11, 2006Google Scholar
  37. 37.
    K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, B. Zheng, M. Bohr, “A 3 GHz 70 Mb SRAM in 65 nm CMOS Technology with Integrated column-Based Dynamic Power Supply” IEEE Journal of Solid-State Circuits, Volume 3.1, number. 1, 2006Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  1. 1.Fukuoka Institute of TechnologyFukuokaJapan

Personalised recommendations