Embedded Memory Architecture for Low-Power Application Processor

  • Hoi Jun Yoo
  • Donghyun Kim
Part of the Integrated Circuits and Systems book series (ICIR)

Currently, the state-of-the-art high-end processors operate at 3–4 GHz frequency whereas even the fastest off-chip memory operates at just around 600 MHz [1, 2, 3, 4, 5, 6]. In decades, along with advances in processor technology, the speed gap between processors and memories has become intolerably large [7], and this speed gap has driven the processor designers to introduce a memory hierarchy into the processor architecture. For processors, it is ideal to have indefinitely large memory with no access latencies [8]. However, implementing large-capacity memory with fast operation speed is infeasible due to the physical limitations of the electrical circuits. Thus, the capacity is usually traded off with the operation speed in memory designs. For example, on-chip L1 caches are able to operate as fast as the state-of-the-art processor cores but have at most few kilobytes capacity. On the other hand, off-chip DRAMs are capable of storing few gigabytes though their operation frequencies are just around hundreds of megahertz.


Hard Disk Drive Memory Hierarchy Data Transaction Frame Buffer Very Long Instruction Word 
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Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  • Hoi Jun Yoo
  • Donghyun Kim

There are no affiliations available

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