The previous chapters were based on a relatively straight-forward understanding of how the Verilog simulator schedules and executes events. This chapter develops a more detailed model of the simulator, including the processing of a number of the more subtle timing semantics of the language. Topics include the simulator scheduling algorithm, non-deterministic aspects of the language, and non-blocking assignments.
The material in this chapter is meant to explain conceptually how Verilog simulators are expected to work. However, the presentation may not match any particular implementation. There are plenty of short-cuts, tricks, and go-fasts that are or could be implemented. Their mileage and software-engineering appropriateness may vary and are not the topic of the chapter.
KeywordsEvaluation Event Behavioral Model Clock Period Advance Timing Simulation Cycle
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