We now turn our attention to a higher level of modeling: cycle accurate, sometimes called scheduled behavior. At this level, a system is described in a clock-cycle by clock-cycle fashion, specifying the behavior that is to occur in each state. The term cycle-accurate is used because the values in the system are specified to be valid only at the time of the system’s state change — at a clock edge. This chapter presents the cycle-accurate method of specification, overviews behavioral synthesis, and illustrates how to specify systems for design using behavioral synthesis.
KeywordsClock Cycle Finite State Machine Data Path Clock Period Loop Body
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