The exercises at the end of the previous chapters have been short questions to help you think about the material in the chapter. This chapter contains two projects that each encompass many aspects of the Verilog language. Each of these projects has been used in Junior level university classes for electrical and computer engineering students.

The projects are all open-ended; there is no one correct answer. Instructors should realize that the projects were aimed at a set of students with a certain course background that may not match the background of their current students. Further, the projects were tailored to the specific material being presented in class at the time. Alter the projects by adding or deleting portions as needed.

Some of these projects have supporting Verilog descriptions. These may be obtained from the e-mail reflector as described in the book’s Preface.


Clock Signal Clock Period Direct Memory Access Clock Pulse NAND Gate 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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© Springer Science+Business Media, LLC 2008

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