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Phase Change Random Access Memory Integration

  • Matthew J. Breitwisch

Abstract

This chapter reviews the basic process integration and structural design issues regarding the phase change random access memory cell. Basic memory cell design, phase change device characteristics and access device requirements will be reviewed, and then a detailed discussion of the phase change memory device design follows. Various cell designs, including the mushroom cell, cell, μTrench cell and pore cell will be evaluated in terms of RESET current (the current to switch the cell to the amorphous state by melting and rapidly quenching) and RESET current variability minimization. Finally, multi-level phase change random access memory will be discussed.

Keywords

Phase Change Phase Change Material Bottom Electrode Titanium Nitride Field Effect Transistor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [17.1]
    Kang, S., Cho, W. Y., Cho, B. H., Lee, K. J., Lee, C. S., Oh, H. R., Choi, B. G., Wang, Q., Kim, H. J., Park, M. H., Ro, Y. H., Kim, S., Ha, C. D., Kim, K. S., Kim, Y. R., Kim, D. E., Kwak, C. K., Byun, H. G., Jeong, G., Jeong, H., Kim, K. and Shin, Y.: A 0.1-μ 1.8-V 256-Mb phase change random access memory (PRAM) with 66-Mhz synchronous burst-read operation. IEEE Journal of Solid-State Circuits42, 210-218 (2007)CrossRefGoogle Scholar
  2. [17.2]
    Rajendran, B., Lee, M. H., Breitwisch, M., Burr, G. W., Shih, Y. H., Cheek, R., Schrott, A., Chen, C. F., Lamorey, M., Joseph, E., Zhu, Y., Dasaka, R., Flaitz, P. L., Baumann, F. H., Lung, H. L., and Lam, C.: On the dynamic resistance and reliability of phase change memory. VLSI (2008)Google Scholar
  3. [17.3]
    Pirovano, A., Redaelli, A., Pellizzer, F., Ottogalli, F., Tosi, M., Ielmini, D., Lacaita, A. L., and Bez, R.: Reliability study of phase change nonvolatile memories. IEEE Transactions on Device and Materials Reliability, 4(3):422-427 (2004)CrossRefGoogle Scholar
  4. [17.4]
    Oh, J. H., Park, J. H., Lim, Y. S., Lim, H. S., Oh, Y. T., Kim, J. S., Shin, J. M., Park, J. H., Song, Y. J., Ryoo, K. C., Lim, D. W., Park, S. S., Kim, J. I., Kim, J. H., Yu, J., Yeung, F., Jeong, C. W., Kong, J. H., Kang, D. H., Koh, G. H., Jeong, G. T., Jeong, H. S., and Kim, K.: Full integration of highly manufacturable 512 Mb PRAM based on 90 nm technology. IEDM, San Francisco, CA, p. 49-53 (2006)Google Scholar
  5. [17.5]
    Lung, H. L, Breitwisch, M., Happ, T., and Lam, C.: Phase change memory – present and future. Int. Conf. on Memory Technology and Design, Giens, France (2007)Google Scholar
  6. [17.6]
    Pellizzer, F., Benvenuti, A., Gleixner, B., Kim, Y., Johnson, B., Magistretti, M., Marangon, M., Pirovano, A., Bez, R., and Atwood, G.: A 90 nm phase change memory technology for stand-alone non-volatile memory applications. In Symposium on VLSI Technology, pages 122-123 (2006)Google Scholar
  7. [17.7]
    Oh, J. H., Park, J. H., Lim, Y. S., Lim, H. S., Oh, Y. T., Kim, J. S., Shin, J. M., Park, J. H., Song, Y. J., Ryoo, K. C., Lim, D. W, Park, S. S., Kim, J. I., Kim, J. H., Yu, J., Yeung, F., Jeong, C. W., Kong, J. H., Kang, D. H., Koh, G. H., Jeong, G. T., Jeong, H. S., and Kim, K.: Full integration of highly manufacturable 512 Mb PRAM based on 90 nm technology. In IEDM Technical Digest, page 2.6 (2006)Google Scholar
  8. [17.8]
    Raoux, S., Burr, G. W., Breitwisch, M. J., Rettner, C. T., Chen, Y. C., Shelby, R. M., Salinga, M., Krebs, D., Chen, S. H., Lung, H. L., and Lam, C. H.: Phase change random access memory — a scalable technology. IBM J. Res. & Dev.52, 465-480 (2008)CrossRefGoogle Scholar
  9. [17.9]
    Lai, S. and Lowrey, T.: OUM - a 180 nm nonvolatile memory cell element technology for stand alone and embedded applications: International Electron Devices Meeting. Technical Digest Washington, DC, USA 2-5 Dec. 2001, p. 3651-3654 (2001)Google Scholar
  10. [17.10]
    Ahn, S. J., Hwang, Y. N., Song, Y. J., Lee, S. H., Lee, S. Y., Park, J. H., Jeong, C. W., Ryoo, K. C., Shin, J. M., Park, J. H., Fai, Y., Oh, J. H., Koh, G. H., Jeong, G. T., Joo, S. H., Choi, S. H., Son, Y. H., Shin, J. C., Kim, Y. T., Jeong, H. S., and Kim, K.: Highly reliable 50 nm contact cell technology for 256 Mb PRAM. Symposium on VLSI Technology Digest of Technical Papers, p. 98-99 (2005)Google Scholar
  11. [17.11]
    Jeong, C. W., Ahn, S. J., Hwang, Y. N., Song, Y. J, Oh, J. H., Lee, S. Y., Lee, S. H., Ryoo, K. C., Park, J. H., Park, J. H., Shin, J. M., Yeung, F., Jeong, W. C., Kim, J. I., Koh, G. H., Jeong, G. T., Jeong, H. S., and Kim, K.: Highly reliable ring-type contact for high-density phase change memory. Jap. J. Appl. Phys. 45, 3233-3237 (2006)CrossRefGoogle Scholar
  12. [17.12]
    Song, Y. J., Ryoo, K. C., Hwang, Y. N., Jeong, C. W., Lim, D. W., Park, S. S., Kim, J. I., Kim, J. H., Lee, S. Y., Kong, J. H., Ahn, S. J., Lee, S. H., Park, J. H., Oh, J. H., Oh, Y. T, Kim, J. S., Shin, J. M., Park, J. H., Fai, Y., Koh, G. H., Jeong, G. T., Kim, R. H., Lim, H. S., Park, I. S., Jeong, H. S., and Kim, K.: Highly reliable 256 Mb PRAM with advanced ring contact technology and novel encapsulating technology: Symposium on VLSI Technology, p. 15-16 (2006)Google Scholar
  13. [17.13]
    Ryoo, K. C., Song, Y. J., Shin, J. M., Park, S. S., Lim, D. W., Kim, J. H., Park, W. I., Sim, K. R., Jeong, J. H., Kang, D. H., Kong, J. H., Jeong, C. W., Oh, J. H., Park, J. H., Kim, J. I., Oh, Y. T., Kim, J. S., Eun, S. H., Lee, K. W., Koh, S. P., Fai, Y., Koh, G. H., Jeong, G. T., Jeong, H. S., and Kim, K.: Ring contact electrode process for high density phase change random access memory. Jap. J. Appl. Phys. 46, p. 2001-2005 (2007)CrossRefGoogle Scholar
  14. [17.14]
    Happ, T. D., Breitwisch, M., Schrott, A., Philipp, J. B., Lee, M. H., Cheek, R., Nirschl, T., Lamorey, M., Ho, C. H., Chen, S. H., Chen, C. F., Joseph, E., Zaidi, S., Burr, G. W., Yee, B., Chen, Y. C., Raoux, S., Lung, H. L, Bergmann, R., and Lam, C.: Novel one-mask self-heating pillar phase change memory. Symp. on VLSI Technology, Honolulu, Hawaii, p. 15-16 (2006)Google Scholar
  15. [17.15]
    Chen, Y. C., Rettner, C. T., Raoux, S., Burr, G. W., Chen, S. H., Shelby, R. M., Salinga, M., Risk, W. P., Happ, T. D., McClelland, G. M., Breitwisch, M., Schrott, A., Philipp, J. B., Lee, M. H., Cheek, R., Nirschl, T., Lamorey, M., Chen, C. F., Joseph, E., Zaidi, S., Yee, B., Lung, H. L., Bergmann, R., and Lam, C.: Ultra-thin phase-change bridge memory device using GeSb. IEDM Technical Digest, San Francisco, CA, p. S30P3 (2006)Google Scholar
  16. [17.16]
    Pellizzer, F., Pirovano, A., Ottogallic, F., Magistretti, M., Scaravaggi, M., Zuliani, P., Tosi, M., Benvenuti, A., Besana, P., Cadeo, S., Marangon, T., Morandi, R., Piva, R., Spandre, A., Zonca, R., Modelli, A., Varesi, E., Lowrey, T., Lacaita, A., Casagrande, G., Cappelletti, P., and Bez, R.: Novel ?-trench phase-change memory cell for embedded and stand-alone non-volatile memory applications. Symposium on VLSI Technology, p. 18-19 (2004)Google Scholar
  17. [17.17]
    Tyson, S., Wicker, G., Lowrey, T., Hudgens, S., and Hunt, K.: Nonvolatile, high density, high performance phase change memory. IEEE Aerospace Conference Proceedings, Vol. 5, Big Sky, MT, USA, 18-25 March 2000, p. 385-390 (2000)Google Scholar
  18. [17.18]
    Cho, S. L., Yi, J. H., Ha, Y. H., Kuh, B. J., Lee, C. M., Park, J. H., Nam, S. D., Horii, H., Cho, B. O., Ryoo, K. C., Park, S. O., Kim, H. S., Chung, U. I., Moon, J. T., and Ryu, B. I.: Highly scalable on-axis confined cell structure for high density PRAM beyond 256 Mb. Symp. on VLSI Technology Digest of Technical Papers, p. 96-97 (2005)Google Scholar
  19. [17.19]
    Breitwisch, M., Nirschl, T., Chen, C. F., Zhu, Y., Lee, M. H., Lamorey, M., Burr, G. W., Joseph, E., Schrott, A., Philipp, J. B., Cheek, R., Happ, T. D., Chen, S. H., Zaidi, S., Flaitz, P., Bruley, J., Dasaka, R., Rajendran, B., Rossnagel, S., Yang, M., Chen, Y. C., Bergmann, R., Lung, H. L., and Lam, C.: Novel lithography-independent pore phase change memory. Symposium on VLSI Technology, p. 6B-3 (2007)Google Scholar
  20. [17.20]
    Lee, J. I., Park, H., Cho, S. L., Park, Y. L., Bae, B. J., Park, J. H., Park, J. S., An, H. G., Bae, J. S., Ahn, D. H., Kim, Y. T., Horii, H., Song, S. A., Shin, J. C., Park, S. O., Kim, H. S., Chung, U. I., Moon, J. T., and Ryu, B. I.: Highly scalable phase change memory with CVD GeSbTe for sub 50 nm generation. Symp. on VLSI Technology, Kyoto, Japan, p. 102-103 (2007)Google Scholar
  21. [17.21]
    Czubatyj, W., Lowrey, T., Kostylev, S., and Asano, I.: Current reduction in Ovonic memory devices. Proc. Europ. Phase Change and Ovonic Science Symp., Grenoble, France, p. 143-152 (2006)Google Scholar
  22. [17.22]
    Lee, S., Song, Y. J., Hwang, Y. N., Lee, S. H., Park, J. H., Ryoo, K. C., Ahn, S. J., Jeong, C. W., Oh, J. H., Shin, J. M., Yeung, F., Jeong, W. C., Kim, Y. T., Park, J. B., Koh, K. H., Jeong, G. T., Jeong, H. S., and Kim, K.: Effect of the bottom electrode contact (BEC) on the phase transformation of N2 doped Ge2Sb2Te5 (N-GST) in a phase-change random access memory. In MRS Proceedings, volume 830, page D7.9.1 (2005)Google Scholar
  23. [17.23]
    Pirovano, A., Lacaita, A. L., Benvenuti, A., Pellizzer, F., Hudgens, S., and Bez, R.: Scaling analysis of phase-change memory technology. IEDM Tech. Dig. p. 699-703 (2003)Google Scholar
  24. [17.24]
    Kim, Y, T., Hwang, Y. N., Lee, K. H., Lee, S. H., Jeong, C. W., Ahn, S. J, Yeung, F., Koh, G. H., Jeong, H. S., Chung, W. Y., Kim, T. K., Park, Y. K., Kim, K. N., and Kong, J. T.: Programming characteristics of phase change random access memory using phase change simulations. Jap. J. Appl. Phys. 44, 2701-2705 (2005)CrossRefGoogle Scholar
  25. [17.25]
    Lankhors, M. H. R., Ketelaars, B. W. S. M. M., and Wolters, R. A. M.: Low-cost and nanoscale non-volatile memory concept for future silicon chips.: Nature Mater. 4, 347-352 (2005)CrossRefGoogle Scholar
  26. [17.26]
    Joseph, E. A., Happ, T. D., Chen, S. H., Raoux, S., Totir, G., Pyzyna, A., Chen, C. F., Breitwisch, M., Schrott, A. G., Zaidi, S., Dasaka, R., Yee, B., Zhu, Y., Bergmann, R., Lung, H. L., and Lam, C.: Patterning of N:Ge2Sb2Te5 films and the characterization of etch induced modification for non-volatile phase change memory applications. VLSI TSA (2008)Google Scholar
  27. [17.27]
    Bedeschi, F., Fackenthal, R., Resta, C., Donze, E., Jagasivamani, M., Buda, E., Pellizzer, F., Chow, D., Fantini, A., Calibrini, A., Calvi, G., Faravelli, R., Torelli, G., Mills, D., Gastaldi, R., and Casagrande, G.: A multi-level-cell bipolar-selected phase-change memory. In ISSCC Technical Digest, volume paper 23.5 (2008)Google Scholar
  28. [17.28]
    Nirschl, T., Philipp, J. B., Happ, T. D., Burr, G. W., Rajendran, B., Lee, M. H., Schrott, A., Yang, M., Breitwisch, M., Chen, C. F., Joseph, E., Lamorey, M., Cheek, R., Chen, S. H., Zaidi, S., Raoux, S., Chen, Y. C., Zhu, Y., Bergmann, R., Lung, H. L., and Lam, C.: write strategies for 2 and 4-bit multi-level phase-change memory. Int. Electron Devices Meeting, Washington, DC (2007)Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  1. 1.IBM T. J. Watson Research CenterYorktown Heights

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