Advertisement

Phase Change Random Access Memory Advanced Prototype Devices and Scaling

  • Yi-Chou Chen

Abstract

This chapter describes the design, fabrication, and testing of advanced prototype Phase Change Random Access Memory (PCRAM) devices that have been used to study the scaling behavior of PCRAM. It compares various PCRAM designs and summarizes what has been learned from the performance of these devices regarding the switching properties and scaling behavior of PCRAM. In addition, specific test equipment and test procedures for the characterization of PCRAM are described.

Keywords

Phase Change Phase Change Material Bottom Electrode Chemical Mechanical Polishing Device Under Test 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [15.1]
    Baker, R.J.: CMOS Circuit Design, Layout, and Simulation. 2nd edition, pp.181-182, IEEE Press (2005)Google Scholar
  2. [15.2]
    Wolf, S.: Silicon Processing for the VLSI Era. Vol. 3: The submicron MOSFET, pp. 307, Lattice Press (1995)Google Scholar
  3. [15.3]
    Chen, M.L., Leung, C.W., Cochran, W.T., Harney, R., Maury, A. and Hey, H.P.W.: A high performance submicron CMOS process with self-aligned channel-stop and punch through implants (Twin-Tub V), IEDM Tech. Dig., 256-259 (1986)Google Scholar
  4. [15.4]
    Lai, S., Lowrey, T.: OUM-A 180 nm nonvolatile memory cell element technology for stand alone and embedded applications. IEDM Tech. Dig., 803-806 (2001)Google Scholar
  5. [15.5]
    Lai, S.: Current status of the phase change memory and its future. IEDM Tech. Dig., 255-258 (2003)Google Scholar
  6. [15.6]
    Pirovano, A., Lacaita, A.L., Benvennuti, A., Pellizzer, F., Hudgens, S. and Bez, R.: Scaling analysis of phase-change memory technology. IEDM Tech. Dig., 699-702 (2003)Google Scholar
  7. [15.7]
    Matsui, Y., Kurotsuchi, K., Tonomura, O., Morikawa, T.,Kinoshita, M., Fujisaki, Y., Matsuzaki, N., Hanzawa, S., Terao., M., Takaura, N., Moriya, H., Iwasaki, T., Moniwa, M. and Koga, T.: Ta2O5 interfacial layer between GST and W plug enabling low power operation of phase change memories. IEDM Tech. Dig., 769-772 (2006)Google Scholar
  8. [15.8]
    Cabral, C. Jr., Chen, K.N., Krusin-Elbaum, L. and Deline, V.: Irreversible modification of Ge2Sb2Te5 phase change material by nanometer-thin Ti adhesion layers in a device-compatible stack. Appl. Phys. Lett. 90, 51908-51910 (2007)CrossRefGoogle Scholar
  9. [15.9]
    Hwang, Y.N., Hong, J.S., Lee, S.H., Ahn, S.J, Jeong, G.T., Koh, G.H., Oh, J.H., Kim, H.J., Jeong, W.C., Lee, S.Y., Park, J.H., Ryoo, K.C., Horii, H., Ha, Y.H., Yi, J.H., Cho, W.Y., Kim, Y.T, Lee, K.H., Joo, S.H., Park, S.O., Chung U.I., Jeong, H.S. and Kim, K.: Full integration and reliability evaluation of phase-change RAM based on 0.24 μm-CMOS technologies. Symp. on VLSI Tech. Dig., 173-174 (2003)Google Scholar
  10. [15.10]
    Hwang, Y.N., Lee,, S.H., Ahn, S.J, Lee, S.Y., Ryoo, K.C., Hong, H.S., Koo, H.C., Yeung, F., Oh, J.H., Kim, H.J., Jeong, W.C., Park, J.H., Horii, H., Ha, Y.H., Yi, J.H.Koh, G.H., Jeong, H.S. and Kim, K: Writing current reduction for high-density phase-change RAM, IEDM Tech Dig., 893-896 (2003)Google Scholar
  11. [15.11]
    Chen, Y.C., Chen, C.T., Yu, J.Y., Lee, C.Y., Chen, C.F., Lung, S.L. and Liu, R.: 180 nm Sn-Doped Ge2Sb2Te5 chalcogenide phase-change memory device for low power, high speed embedded memory for SoC applications. Proc. of Custom Integrated Circuits Conference (CICC), 395-398 (2003)Google Scholar
  12. [15.12]
    Matsuzaki, N., Kurotsuchi, K., Matsui, Y., Tonomura, O., Yamamoto, N., Fujisaki, Y., Kitai, N., Takemura, R., Osaka, K., Hanzawa, S., Moriya, H., Iwasaki, T., Kawahara, T., Takaura, N., Terao, M., Matsuoka, M. and Moniwa, M.: Oxygen-doped GeSbTe Phase-change memory cells featuring 1.5 V/100 μA standard 0.13-μm CMOS operations. IEDM Tech. Dig., 757-780 (2005)Google Scholar
  13. [15.13]
    Morikawa, T., Kurotsuchi, K., Kinoshita, M., Matsuzaki, N., Matsui, Y., Fujisaki, Y., Hanzawa, S., Kotabe, A., Terao, M., Moriya, H., Iwasaki, T., Matsuoka, M., Nitta, F., Moniwa, M., Koga, T. and Takaura, N.: Doped In-Ge-Te phase change memory featuring stable operation and good data retention. IEDM Tech. Dig., 307-340 (2007)Google Scholar
  14. [15.14]
    Ahn, S.J., Song, Y.J., Jeong, C.W., Shin, J.M., Fai, Y., Hwang, Y.N., Lee, S.H., Ryoo, K.C., Lee, S.Y., Psrk, J.H., Horii, H., Ha, Y.H., Yi, J.H., Kuh, B.J., Koh, G.H., Jeong, G.T., Jeong, H.S., Kim, K. and Ryu, B.I.: Highly manufacturable high density phase change memory of 64 Mb and beyond. IEDM Tech. Dig., 907-910 (2004)Google Scholar
  15. [15.15]
    Oh, J.H., Park, J.H. Lim, Y.S., Lim, H.S., Oh, Y.T., Kim, J.S., Shin, J.M., Park, J.H., Song, Y.J., Ryoo, K.C., Lim, D.W., Park, S.S., Kim, J.I., Yu, J., Yeung, F., Jeong, C.W., Kong, J.H., Kang, D.H., Koh, G.H., jeong, G.T., Jeong, H.S. and Kim, K.: Full integration of highly manufacturable 512 Mb PRAM based on 90 nm technology. IEDM Tech. Dig., 49-52 (2006)Google Scholar
  16. [15.16]
    Ha, Y.H., Yi, J.H., Horii, H., Park, J.H., Joo, S.H., Park, S.O., Chung, U.-I. and Moon, J.T.: An edge contact type cell for phase change RAM featuring very low power consumption. Symp. on VLSI Tech. Dig., 175-176 (2003)Google Scholar
  17. [15.17]
    Yi, J.H., Ha, Y.H., Park, J.H., Kuh, B.J., Horii, H., Kim, Y.T., Park, S.O., Hwang, Y.N., Lee, S.H., Ahn, S.J., Lee, S.Y., Hong, J.S., Lee, K.H., Lee, N.I., Kang, H.K., Chung, U.-I,, Moon, J.T.: Novel cell structure of PRAM with thin metal layer inserted GeSbTe. IEDM Tech. Dig. 901-904 (2003)Google Scholar
  18. [15.18]
    Pellizzer,F., Pirovano, A., Ottogalli, F., Magistretti, M., Scaravaggi ,M., Zuliani, P., Tosi, M., Ben-venuti, A., Besana, P., Cadeo, S., Marangon, T., Morandi, R., Piva, R., Spandre, A., Zonca, R., Mod-elli, A., Varesi, E., Lowrey, T., Lacaita, A., Casagrande, G., Cappelletti, P. and Bez, R.: Novel μ–trench phase-change memory cell for embedded and stand-alone nonvolatile memory applications. Symp. on VLSI Tech. Dig., 18–19 (2004)Google Scholar
  19. [15.19]
    Bedeschi, F., Bez, R., Boffino, C., Bonizzoni, E., Buda, E.C., Casagrande, G., Costa, L., Ferraro, M., Gastaldi, R., Khouri, O., Ottogalli, F., Pellizer, F., Pirovano, A., Resta, C;, Torelli, G. and Tosi, M.: 4-Mb MOSFET-Selected μ-trench phase change memory experimental chip. IEEE J. Solid-State. Cir. 40, 1557-1565 (2005)CrossRefGoogle Scholar
  20. [15.20]
    Pellizzer, F., Benvenuti, A., Gleixner, B., Kim, Y., johnson, B., Magistretti, M., Marangon, T., Pirovano, A., Ben, R. and Atwood, G.: A 90 nm phase change memory technology for stand-alone non-volatile memory applications. Symp. on VLSI Tech. Dig., 122-123 (2006)Google Scholar
  21. [15.21]
    Mantegazza, D., Ielmini, D., Varesi, E., Pirovano, A. and Lacaita, A.L.: Statistical analysis and modeling of programming and retention in PCM arrays. IEDM Tech. Dig., 311-314 (2007)Google Scholar
  22. [15.22]
    Ielmini, D., Lavizzari, S., Sharma, D. and Lacaita, A.L.: Physical interpretation, modeling and impact on phase change memory (PCM) reliability of resistance drift due to chalcogenide structural relaxation. IEDM Tech. Dig., 939-942 (2007)Google Scholar
  23. [15.23]
    Ahn, S.J., Hwang, Y.N., Song, Y.J., Lee, S.H., Leee, S.Y., Park, J.H., Jeong, C.W., Ryoo, K.C., Shin, J.M., Park, J.H., Fai, Y., Oh, J.H., Koh, G.H., Jeong, G.T., Joo, S.H., Choi, S.H., Son, Y.H., Shin, J.C., Kim, Y.T., Jeong, H.S. and Kim, K.: Highly reliable 50 nm contact cell technology for 256 Mb PRAM. Symp. on VLSI Tech. Dig., 98-99 (2005)Google Scholar
  24. [15.24]
    Jeong, C.W., Ahn, S.J., Hwang, Y.N., Song, Y.J., Oh, J.H., Lee, S.Y., Lee, S.H., Ryoo, K.C., Park, J.H., Shin, J.M., Park, J.H., Yeung, F., Jeong, W.C., Kim, Y.T., Koh., K.H., Jeong, G.T., Jeong, H.S. and Kim, K.N.: Highly reliable ring type contact scheme for high density PRAM. Int. Conf. on Solid State Devices and Mat., 1048-1049 (2005)Google Scholar
  25. [15.25]
    Song, Y.J., Ryoo, K.C., Hwang, Y.N., Jeong, C.W., Lim, D.W., Park, S.S., Kim, J.I., Kim, J.H., Lee, S.Y., Kong, J.H., Ahn, S.J., Lee, S.H., Park, J.H., Oh., J.H., Oh, Y.T., Kim, J.S., Shin, J.M., Park, J.H., Fai, Y., Koh, G.H., Jeong, G.T., Kim, R.H., Lim, H.S., Park, I.S., Jeong, H.S. and Kim, K: Highly reliable 256 Mb PRAM with advanced ring contact technology and novel encapsulating technology. Symp. on VLSI Tech. Dig., 118-119 (2006)Google Scholar
  26. [15.26]
    Kang, D.H., Kim, J.S., Kim, Y.R., Kim, Y.T., Lee, M.K., Jun, Y.J., Park, J.H., Yeung, F., Jeong, C.W., Yu, J., Kong, J.H., Ha, D.W., Song, S.A., Park, Y.H., Song, Y.J., Eum, C.Y., Ryoo, K.C., Shin, J.M., Lim, D.W., Park, S.S., Kim., J.H., Park, W.I., Sim, K.R., Cheong, J.H., Oh, J.H., Oh, J.H., Park, J.H., Kim, J.I., Oh, Y.T., Lee, K.W., Koh, S.P., Eun, S.H., Kim, N.B., koh, G.H., Jeong, G.T., Jeong, H.S. and Kim, K: Novel heat dissipating cell scheme for improving a reset distribution in a 512 Mb phase-change random access memory (PRAM). Symp. on VLSI Tech. Dig., 96-97 (2007)Google Scholar
  27. [15.27]
    Oh, J.H., Park, J.H., Lim, Y.S., Lim, H.S., Oh, Y.T., Kim, J.S., Shin, J.M., Oark, J.H., Song, Y.J., Ryoo, K.C., Lim, D.W., Park, S.S., Kim, J.I., Kim, J.H., Yu, J., Yeung, F., Jeong, C.W., Kong, J.H., Kang, D.H., Koh, G.H., Jeong, G.T., Jeong, H.S. and Kim, K.: Full integration of highly manufacturable 512 Mb PRAM based on 90 nm technology. IEDM Tech. Dig., 49-52 (2006)Google Scholar
  28. [15.28]
    Happ, T., Breitwisch, M., Schrott, A., Philipp, J., Lee, M., Cheek, R., Nirschl, T., Lamorey, M., Ho, C., Chen, S., Chen, C., Joseph, E., Zaidi, S., Burr, G., Yee, B., Chen, Y.C., Raoux, S., Lung, H., Bergmann, R. and Lam, C.: Novel one-mask self-heating pillar phase change memory. Symp. on VLSI Tech. Dig., 120-121 (2006)Google Scholar
  29. [15.29]
    Lankhorst, M.H.R, Ketelaars, B.W.S.M.M. and Wolters, R.A.M.: Low-cost and nanoscale non-volatile memory concept for future silicon chips. Nature Mater., 4, 347-352 (2005)CrossRefGoogle Scholar
  30. [15.30]
    Redaelli, A., Ielmini, D., Lacaita, A.L., Pellizzer, F. and Ben, R.: Impact of crystallization statistics on data retention for phase change memories. IEDM Tech. Dig., 761-764 (2005)Google Scholar
  31. [15.31]
    Chen, Y.C., Rettner, C.T., Raoux, S., Burr, G.W., Chen, S.H., Shelby, R.M., Salinga, M., Risk, W.P., Happ, T.D., McCleland, G.M., Breitwisch, M., Schrott, A., Philipp, J.B., Lee, M.H., Cheek, R., Nirschl, T., Lamorey, M., Checn, C.F., Joseph, E., Zaidi, S., Yee, B., Lung, H.L., Bergmann, R. and Lam, C.: Ultra-thin phase-change bridge memory device using GeSb. IEDM Tech. Dig., 777-780 (2006)Google Scholar
  32. [15.32]
    Raoux, S., Rettner, C.T., Jordan-Sweet, J.L., Deline, V.R., Philipp, J.B. and Lung, H.L.: Scaling properties of phase change nanostructures and thin films. European Phase Change and Ovonics Symposium (2006), http://www.epcos.org/papers/pdf_2006/pdf_Invited/Raoux.pdf Accessed 20 Feb. 2008
  33. [15.33]
    Raoux, S., Rettner, C.T., Chen, C.T., Jordan-Sweet, J., Zhang, Y., Caldwell, M., Wong, H.-S.P., Milliron, D. and Cha, J.: Scaling properties of phase change materials. Non-Volatile Memory Tech. Symp. 2007, 30-35 (2007)Google Scholar
  34. [15.34]
    Castro, D.T., Goux, L., Hurkx, G.A.M., Attenborough, K., Delhouhne, R., Lisoni, J., Jedema, F.J., int Zandt, M.A.A., Wolters, R.A.M., Gravesteijn, D.J., Verheijen, M.A., Kaiser, M., Weemaes, R.G.R. and Wouters., D.J.: Evidence of the thermo-electric Thomson effect and influence on the program conditions and cell optimization in phase-change memory cells. IEDM Tech. Dig., 315-318 (2007)Google Scholar
  35. [15.35]
    Chen, W.S., Lee, C.M., Chao, D.S., Chen, Y.C., Chen, F., Chen, C.W.,Yen, P.H., Chen, M.J., Wang, W.H., Hsiao, T.C., Yeh, J.T., Chiou, S.H., Liu, M.Y., Wang, T.C., Chein, L.L., Huang, C.M., Shih, N.T., Tu, L.S., Huang, D., Yu, T.H., Kao, M.J. and Tsai, M.-J.: A novel cross-spacer phase change memory with ultra-small lithography independent contact area. IEDM Tech. Dig., 319-322 (2007)Google Scholar
  36. [15.36]
    Ovonic Unified Memory, http://ovonyx.com/technology/technology.pdf (1999). Accessed 20 Feb. 2008
  37. [15.37]
    Nirschl, T., Philipp, J.B., Happ, T.D., Burr, G.W., Rajendran, B., Lee, M.-H., Schrott, A., Yang, M., Breitwisch, M., Chen, C.-F., Joseph, E., Lamorey, M., Cheek, R., Chen, S.-H., Zaidi, S., Raoux, S., Chen, Y.C., Zhu, Y., Bergmann, R., Lung, H.-L. and Lam, C.: Write Strategies for 2 and 4-bit multi-level phase-change memory. IEDM Tech. Dig., 461-464 (2007)Google Scholar
  38. [15.38]
    M. Breitwisch, M., Nirschl, T., Chen, C.F., Zhu, Y., Lee, M.H., Lamorey, M., Burr, G.W., Joseph, E., Schrott, A., Philipp, J.B., Cheek, R., Happ, T.D., Chen, S.H., Zaidi, S., Flaitz, P., Bruley, J., Dasaka, R., Rajendran, B., Rossnagel, S., Yang, M., Chen, Y.C., Bergmann, R., Lung, H.L. and Lam., C.: Novel lithography-independent pore phase change memory. Symp. on VLSI Tech Dig., 100-101(2007)Google Scholar
  39. [15.39]
    Cho, S.L., Yi, J.H., Ha, Y.H., Kuh, B.J., Lee, C.M., Park, J.H., Nam, S.D., Horii, H., Cho, B.O., Ryoo, K.C., Park, S.O., Kim, H.S., Chung, U.I., Moon, J.T. and Ryu, B.I.: Highly scalable on-axis confined cell structure for high density PRAM beyond 256 Mb. Symp. on VLSI Tech. Dig., 96-97 (2005)Google Scholar
  40. [15.40]
    Kencke, D.L., Karpov, I.V., Johnon, B.G., Lee, S.J., Kau, D., Hudgens S.J., Reifenberg, J.P., Savransky, S.D., Giles, M.D. and Spadini, G.: The role of interfaces in Damascene phase-change memory. IEDM Tech. Dig., 323-326 (2007)Google Scholar
  41. [15.41]
    Lee, J.I., Park, H., Ch, S.L., Park, Y.L., Bae, B.J., Park, J.H., Park, J.S., An.H.G., Bae, J.S., Ahn, D.H., Kim, Y.T., Horii, H., Song, S.A., Shin, J.C., Park, S.O., Kim., H.S., Chung, U.I., Moon, J.T., Ryu, B.I.: Highly Scalable Phase Change Memory with CVD GeSbTe for Sub 50 nm Generation, Symp. on VLSI Tech., 102-103 (2007)Google Scholar
  42. [15.42]
    Pirovano, a., Lacaita, A.L., Pellizzer, F., Kostylev, S.A., Benvenuti, A. and Bez, R.: Low-field amorphous state resistance and threshold voltage drift in chalcogenide materials. IEEE Trans. on Electronic Dev., 51, 714-719 (2004)CrossRefGoogle Scholar
  43. [15.43]
    Kurotsuchi, K., Takaura, N., Matsuzaki, N., Matsui, Y., Tonomura, O., Fujisaki, Y., Kitai, N., Takemura, R., Osada, K., Hanzawa, S., Moriya, H., Iwasaki, T., Kawahara, T., Terao, M., Matsuoka, M. and Moniwa, M.: Measurement method for transient programming current of 1T1R phase-change memory. IEEE Int. Conf. on Microelectronic Test Structures, 43-46 (2006)Google Scholar
  44. [15.44]
    Redaelli, A., Lacaita, A.L., Benvenuti, A. and Pirovano, A.: Comprehensive numerical model for phase-change memory simulations. Proceeding of IEEE International Conference on Simulation of Semiconductor Devices and Processes (SISPAD), 280-282 (2005)Google Scholar
  45. [15.45]
    Shaw, M.P. and Gastman, I.J.: Circuit controlled current instabilities in “S-shaped” negative differential conductivity elements. Appl. Phys. Lett. 19, 243-245 (1971)CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  1. 1.Advanced Memory Research Dept. (ME130)Emerging Central Lab, Macronix Int. Co. LtdScience ParkTaiwan

Personalised recommendations