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Test and Diagnostics

  • James Donald Rockrohr
Chapter
HSS devices incorporate features which support various levels of testing by the chip manufacturer, the system manufacturer, and by the end user (as part of a diagnostic test suite). These levels of testing include:
  • JTAG 1149.1/1149.6 Test: The JTAG 1149.1 and 1149.6 standards [1,2] define a method of performing chip-to-chip stuck-fault testing during circuit board manufacture. This requires test structures which must be incorporated in all chips to support this testing.

  • Pseudo-Random Bit Sequence (PRBS) Test: HSS cores generally provide a means of transmitting a PRBS pattern and checking it at the receiver. Such test sequences are used for manufacturing test and characterization of HSS cores, as well as characterization of serial data links in systems.

  • Logic Built-In-Self-Test (LBIST):The chip designer often includes LBIST capabilities on the chip which support in-system diagnostics testing. LBIST implementations are not standardized; each system design team develops their own...

Keywords

Test Pattern Automatic Gain Control Device Under Test Instruction Register Random Jitter 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • James Donald Rockrohr

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