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3D Fabrication Options for High-Performance CMOS Technology

  • Anna W. Topol
  • Steven J. Koester
  • Douglas C. La Tulipe
  • Albert M. Young
Chapter
Part of the Integrated Circuits and Systems book series (ICIR)

3-D Technology

Introduction

The last several decades have seen an incredible increase in the functionality of computational systems. At its core, this capability has been driven by the scaling of semiconductor devices, from fractions of millimeters in the 1960s to tens of nanometers in today’s technologies. The scaling has enabled the number of transistors on a single chip to correspondingly grow at a geometric rate, roughly doubling every 18 months; a trend is that now referred to as Moore’s law [1]. The impact of this trend cannot be underestimated and the resulting increase in computational capacity has had major impacts on almost every facet of society.

For this reason, there is a tremendous push to continue along these same trends. However, several serious roadblocks exist. The first is the limits to lithographic scaling. The second is that power densities will not allow reliable systems to be fabricated even if lithographic scaling could continue. Therefore, it becomes a big...

Keywords

Layer Transfer Static Random Access Memory Power Supply Noise Carrier Wafer Bonding Medium 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgments

The authors wish to thank for their contributions (1) the following IBM personnel: Steven Steen, Kuan-neng Chen, Leathen Shi, Cornelia Tsang, Paul Andry, David Frank, Jyotica Patel, James Vichiconti, Deborah Neumayer, Narender Rana, Robert Trzcinski, Latha Ramakrishnan, Roy Yu, James Tornello, Michael Lofaro, Gill Singco, John Ott, David DiMilia, William Price, Jesus Acevedo, and (2) the following RPI personnel: Dr. James Lu, Dr. Sang Hwui Lee, Dr. Ravi Kumaroh. The authors also acknowledge the support of IBM’s MRL and CSS as well as staff at EV Group and Suss MicroTec.

This project was partially funded by DARPA under contract numbers N66001-00-C-8003 and N66001-04-C-8032.

References

  1. 1.
    Moore G (1965) Cramming more components onto integrated circuits. Electronics 38(8):114–117Google Scholar
  2. 2.
    IBM press release (2007) IBM moves Moore's law into the third-dimension http://www-03.ibm.com/press/us/en/pressrelease/21350.wss
  3. 3.
    Guarini K, Wong, H-SP (2004) Wafer bonding for high performance logic applications. In: Alexe M, Goesele U (eds) Wafer bonding: applications and technology. Springer-Verlag, Berlin, pp 157–160Google Scholar
  4. 4.
    http://www.techsearchinc.com/ (2007) In: Through Silicon Via Technology: The Ultimate Market for 3D Interconnect. TechSearch International Report
  5. 5.
  6. 6.
    Topol AW, Guarini KG, Yu R, Shi L, Newport MR, J. Tornello J, Melick D, O’Neil PA, Colburn M, Singh DV, Cohen GM, Krishna M, Ruiz N, Pogge HB, Ieong M, Purushothaman S, Haensch WE (2003) Demonstration of wafer-level layer transfer of high performance devices and circuits for three-dimensional integrated circuit fabrication. AVS 4th International Conference on Microelectronics and Interfaces, Santa Clara, CA, USA, pp 5–7Google Scholar
  7. 7.
    Jonson SC (2007) 3-D TSV cips take off. Semiconductor International, July, p 40Google Scholar
  8. 8.
    Vardaman J (2007) 3-D Through-silicon vias become a reality. Semiconductor International, June, pp 40–45Google Scholar
  9. 9.
    Andry PS, Tsang C, Sprogis E, Patel C, Wright SL, Webb BC (2006) A CMOS-compatible process for fabricating electrical through-vias in silicon. Proceedings of the 56th Electronic Components and Technology Conference, San Diego, CA, pp 831–837Google Scholar
  10. 10.
    Tsang CK, Topol AW (2006) 3D integrated circuits and silicon carrier packaging realization. Proceedings of 23rd VLSI VMIC Conference, Fremont, CA, September 25–28, 2006, VMIC no 06 IMIC-050 pp 61–69Google Scholar
  11. 11.
    Patel CS, Tsang CK, Schuster C, Doany FE, Nyikal H, Baks CW, Budd R,Buchwalter LP, Andry PS, Canaperi DF, Edelstein DC, Horton R, Knickerbocker JU, Krywanczyk T, Kwark YH, Kwietniak KT, Magerlein JH, Rosner J, Sprogis E (2005) Silicon carrier with deep through vias, fine pitch wiring and through cavity for parallel optical transceiver. Proceedings of the 55th Electronic Components and Technology Conf, Lake Buena Vista, FL, pp 1318–1324Google Scholar
  12. 12.
    Topol AW, Furman BK, Guarini KW, Leathen S, Cohen GM, Walker GF (2004) Enabling technologies for wafer-level bonding of 3D MEMS and integrated circuit structures. 54th Electronic Components and Technology Conference (ECTC), Las Vegas, NV; June 1–4, 2004; vol 1, no s21p2, pp 931–938Google Scholar
  13. 13.
    Chen KN, Tan CS, Fan A, Reif R (2004) Morphology and bond strength of copper wafer bonding. Electrochem Solid-State Lett 7(1):G14–G16,CrossRefGoogle Scholar
  14. 14.
    Chen KN, Tsang CK, Topol AW, Lee SH, Furman BK, Rath DL, Lu J-Q, Young AM, Purushothaman S, Haensch W (2006) Improved manufacturability of Cu bond pads and implementation of seal design in 3D integrated circuits and packages. 23rd International VLSI Multilevel Interconnection (VMIC) Conference, Fremont CA, September 25–28, 2006, VMIC Catalog No 06 IMIC-050, pp 195–202,Google Scholar
  15. 15.
    Chen KN, Lee SH, Andry PS, Tsang CK, Topol AW, Lin YM, Lu JQ, Young AM, Ieong M, Haensch W (2006) Structure design and process control for Cu bonded interconnects in 3D integrated circuits. International Electron Devices Meeting (IEDM) Technical Digest, Session 13.5, pp 20–22Google Scholar
  16. 16.
    Ieong M, Narayana V, Singh D, Topol A, Chan V, Ren Z (2006) Transistor scaling with novel materials and integration. Mater Today 9(6):26–31CrossRefGoogle Scholar
  17. 17.
    Ieong M, Guarini KW, Chan V, Bernstein K, Joshi R, Kedzierski J, Haensch W (2003) Three dimensional CMOS devices and integrated circuits. Proceedings of the IEEE Custom Integrated Circuits Conference, pp 207–213Google Scholar
  18. 18.
    Topol AW, La Tulipe DC, Shi L, Frank DJ, Bernstein K, Steen SE, Kumar A, Singco GU, Young AM, Guarini KW, Ieong M (2006) Three-dimensional integrated circuits. IBM J Res Dev 50(4/5):491–506CrossRefGoogle Scholar
  19. 19.
    Guarini KW, Topol KW, Ieong M, Yu R, Shi L, Newport MR, Frank DJ, Singh DV, Cohen GM, Nitta SV, Boyd DC, O’Neil PA, Tempest SL, Pogge HB, Purushothaman S, Haensch WE (2002) Electrical integrity of state-of-the-art 0.13 lm SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication. IEDM Tech. Digest, pp 943–945Google Scholar
  20. 20.
    La Tulipe D, Shi L, Topol A, Steen S, Pfeiffer D, Posillico D, Neumayer D, Goma D, Vichiconti V, Rubino J, Young A, Ieong M (2006) Critical aspects of layer transfer and alignment tolerances for 3D integration processes. International Conference and Exhibition on Device Packaging (IMAPS), Scottsdale, AZ, March 20–24, 2006, Journal of Microelectronics and Electronic Packaging vol 3, no 1Google Scholar
  21. 21.
    Narayan C, Purushothaman S, Doany F, Deutsch A (1995) Thin film transfer process for low cost MCM-fabrication. IEEE Transactions on Components, Packaging, and Manufacturing Technology (Trans CPMT) Part B, vol 18, no 1, pp 42–46CrossRefGoogle Scholar
  22. 22.
    Ultra Thin Wafer Processing Solutions. June 20, 2007, (http://www.semiconductor.net/web- castsDetail/2140049068.html). Semiconductor International Webcast
  23. 23.
    Topol AW, La Tulipe DC, Shi L, Alam SM, Frank DJ, Steen SE, Vichiconti J, Posillico D, Cobb M, Medd S, Patel J, Goma S, DiMilia D, Robson TM, Duch E, Farinelli M, Wang C, Conti RA, Canaperi DM, Deligianni L, Kumar A, Kwietniak KT, D’Emic C, Ott J, Young AM, Guarini KW, Ieong M (2005) Enabling SOI based assembly technology for three-dimensional (3D) integrated circuits (ICs). IEDM Tech. Digest, pp 363–366Google Scholar
  24. 24.
    Guarini KW, Topol TA, Singh DV, La Tulipe DC, Shi L, Young AM, Alam A, Frank DJ, Neumayer DA, Vichiconti J, Sicina RM, Conti RA, Wang C, Canaperi DM, Deligianni L, Kwietniak KT, Steen SE, Robson M, Gibson GW, Posillico D, Ieong M (2005) Process technologies for three dimensional integration. Proceedings of the 6th Annual International Conference on Microelectronics and Interfaces, American Vacuum Society, pp 212–214Google Scholar
  25. 25.
    Warner K, Burns J, Keast C, Kunz R, Lennon D, Loomis A, Mowers W, Yost D (2002) Low-temperature oxide-bonded three-dimensional integrated circuits. Proceedings of the IEEE International SOI Conference, Oct 7–10 2002, pp 123–125Google Scholar
  26. 26.
    Publications inclue: Tong QY et al (1996) Proceddings of the IEEE International SOI Conference, pp 36–37; Stengl R et al (1989) Jpn J Appl Phys 2810:1735–1741; Tong QY et al (1995) Electrochem Soc Proc 95(7):78–95Google Scholar
  27. 27.
    Steen SE, LaTulipe D, Topol A, Frank D, Belote K, Posillico D (2007) Wafer scale 3D integration: overlay as key to drive potential. Microelec Eng 84(5–8):1412–1415, May–August 2007CrossRefGoogle Scholar
  28. 28.
    Topol AW, La Tulipe DC, Shi L, Alam SM, Young AM, Frank DJ, Steen SE, Vichiconti J, Posillico D, Canaperi DM, Medd S, Conti RA, Goma S, Dimilia D, Wang C, Deligianni L, Cobb MA, Jenkins K, Kumar A, Kwietniak KT, Robson M, Gibson GW, D’Emic C, Nowak E, Joshi R, Guarini KW, Ieong M (2005) Assembly technology for tree dimensional integrated circuits. Proceedings of 22 nd International VLSI Multilevel Interconnection Conference (VMIC), a special conference of 2005 Institute for Microelectronics on Chip Interconnection (IMIC), Fremont CA, Oct 4–6 2005, pp 83–88Google Scholar
  29. 29.
    Tsang CK, Andry PS, Sprogis EJ, Patel CS, Webb BC, Manzer DG, Knickerbocker JU (2006) CMOS-compatible through siIlicon vias for 3D process integration. Pannel Discussion on Enabling Technologies for 3D Integration; MRS Symposium Proceedings November 27–29, 2006 Boston, MA, vol 970, pp 145–153Google Scholar
  30. 30.
    Guarini KW, Topol AT, Ieong M, Bernstein K, Xiu K, Joshi RV, Yu R, Shi L, Newport MR, Singh DV, Cohen GM, Pogge HB, Purushothaman S, Haensch WE (2003) The impact of wafer-level layer transfer on high performance devices and circuits for 3D fabrication. Proceedings of Electrochemical Society (ECS) Annual Meeting, Paris, France, Abstract #431, April 27–May 2, 2003, PV 2003-20, ISBN 1-56677-403-9, In: New Trends in Intercalation Compounds for Energy Storage Conversion (eds) Zaghib K, Julien CM, Prakash J, pp 390–404Google Scholar
  31. 31.
    Joshi RV, Smy T, Banerjee K, Topol A (2007) Thermal dissipation in bonded structures. In: Thermal and Design Issues in 3D ICs, SEMATECH Workshop, October 9–11, 2007, in Albany, NYGoogle Scholar
  32. 32.
    Huang G, Bakir M, Naeemi A, Chen H, Meindl JD (2007) Power delivery for 3D chip stacks: physical modeling and design implication. IEEE 16th Conference on Electrical Performance and Electronic Packaging, Atlanta, October 28–31 2007, Session IX, No 5Google Scholar
  33. 33.
    Huang G, Sekar D, Naeemi A, Shajeri K, Meindl JD (2007) Physical model for power supply noise and chip/package co-design in Gigascale Systems with consideration of hot spots. IEEE Custom Integrated Circuits Conference (CICC), San Jose, September 16–19 2007, no 27.1Google Scholar
  34. 34.
    Iyer S, Barth JE, Parries PC, Norum IP, Rice JP, Logan LR, Hoyniak D (2005) Embedded DRAM: technology platform for the blue gene/L chip. IBM J Res Dev 49(2–3):333–350CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • Anna W. Topol
    • 1
  • Steven J. Koester
  • Douglas C. La Tulipe
  • Albert M. Young
  1. 1.IBM T. J. Watson Research CenterYorktown HeightsUSA

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