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3D Fabrication Options for High-Performance CMOS Technology

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Wafer Level 3-D ICs Process Technology

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Acknowledgments

The authors wish to thank for their contributions (1) the following IBM personnel: Steven Steen, Kuan-neng Chen, Leathen Shi, Cornelia Tsang, Paul Andry, David Frank, Jyotica Patel, James Vichiconti, Deborah Neumayer, Narender Rana, Robert Trzcinski, Latha Ramakrishnan, Roy Yu, James Tornello, Michael Lofaro, Gill Singco, John Ott, David DiMilia, William Price, Jesus Acevedo, and (2) the following RPI personnel: Dr. James Lu, Dr. Sang Hwui Lee, Dr. Ravi Kumaroh. The authors also acknowledge the support of IBM’s MRL and CSS as well as staff at EV Group and Suss MicroTec.

This project was partially funded by DARPA under contract numbers N66001-00-C-8003 and N66001-04-C-8032.

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Authors and Affiliations

  1. IBM T. J. Watson Research Center, Yorktown Heights, NY 10598, USA

    Anna W. Topol

Authors
  1. Anna W. Topol
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  2. Steven J. Koester
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  3. Douglas C. La Tulipe
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  4. Albert M. Young
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Corresponding author

Correspondence to Anna W. Topol .

Editor information

Editors and Affiliations

  1. School Electrical & Electronic Eng., Photonics Res. Centre, Nanyang Technological University, Singapore, 639798, Singapore

    Chuan Seng Tan

  2. Center for Integrated Electronics, Rensselaer Polytechnic Institute, 8th Street 110, Troy, 12180, U.S.A.

    Ronald J. Gutmann

  3. Dept. Electrical Engineering, Massachusetts Institute of Technology, Massachusetts Ave. 77, Cambridge, 02139, U.S.A.

    L. Rafael Reif

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Topol, A.W., Koester, S.J., La Tulipe, D.C., Young, A.M. (2008). 3D Fabrication Options for High-Performance CMOS Technology. In: Tan, C., Gutmann, R., Reif, L. (eds) Wafer Level 3-D ICs Process Technology. Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-76534-1_9

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  • DOI: https://doi.org/10.1007/978-0-387-76534-1_9

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