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Acknowledgments
This authors wish to acknowledge the dedication and persistence of the Microelectronics Laboratory staff and the editorial assistance of Karen Challberg.
The work was sponsored by the Defense Advanced Research Projects Agency under Air Force contract #FA8721-05-C-0002. Opinions, interpretations, conclusions, and recommendations are those of the authors and are not necessarily endorsed by the United States Government.
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Burns, J. et al. (2008). An SOI-Based 3D Circuit Integration Technology. In: Tan, C., Gutmann, R., Reif, L. (eds) Wafer Level 3-D ICs Process Technology. Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-76534-1_8
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