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Cu Wafer Bonding for 3D IC Applications

  • Kuan-Neng Chen
  • Chuan Seng Tan
  • Andy Fan
  • L. Rafael Reif
Chapter
Part of the Integrated Circuits and Systems book series (ICIR)

Introduction

This chapter describes a fabrication method for three-dimensional (3D) integrated circuits (ICs) initially proposed and developed at the Microsystems Technology Laboratories (MTL) at MIT. This work was further refined at IBM T. J. Watson Research Center. Currently, IBM, NTU, MIT, and other institutes are working on this method for use in real 3D applications. This approach to 3D integration is based on metallic wafer bonding, that is, low-temperature direct copper-to-copper (Cu-to-Cu) thermocompression bonding. In subsequent sections of this chapter, we describe low-temperature wafer-to-wafer bonding using Cu as the bonding medium. While most research on the blanket Cu wafer bonding were carried out at MIT, the patterned Cu-bonding studies were developed at IBM. Fundamentals of the bonding mechanism and development of a reliable bonding process are presented. Building on work with Cu wafer bonding, process flow of multilayer stacking of silicon thin films is presented. The...

Keywords

Bonding Process Bond Temperature Bond Quality Wafer Bonding Static Random Access Memory 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgements

The authors wish to thank the contributions and support for the work presented in this chapter from MIT, IBM, RPI, and EV Group. This project was partially funded by DARPA under contract number N66001-04-C-8032.

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Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • Kuan-Neng Chen
    • 1
  • Chuan Seng Tan
  • Andy Fan
  • L. Rafael Reif
  1. 1.IBM T. J. Watson Research CenterYorktown HeightsUSA

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