Stacked CMOS Technologies

  • Mansun Chan
Part of the Integrated Circuits and Systems book series (ICIR)


Active Layer Active Device Silicon Film Wafer Bonding Static Random Access Memory 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    Gibbons JF, Lee KF (1980) One-gate-wide CMOS inverter on laser-recrystallized polysilicon. IEEE Electron Device Lett 1:117–118CrossRefGoogle Scholar
  2. 2.
    Chen CE, Lam HW, Smlhi SDS, Pinizzotto RF (1983) Stacked CMOS SRAM cell. IEEE Electron Device Lett 4:272–274CrossRefGoogle Scholar
  3. 3.
    Colinge JP, Demoulin E, Lobet M (1982) Stacked transistors CMOS (ST-MOS), and nMOS technology modified to CMOS. IEEE Trans Electron Devices 29:585–589CrossRefGoogle Scholar
  4. 4.
    Kunio T, Oyama K, Hayashi Y, Morimoto M (1989) Three-dimensional ICs, having four stacked active device layers. IEDM Tech Dig:837–840Google Scholar
  5. 5.
    Matsamura A, Kawamura K, Hamaguchi I, Takayama S, Yano T, Nagatake Y (1999) Recent progress in low-dose SIMOX wafers fabricated with internal-thermal-oxidation (ITOX) process. Mtg Abs Electrochem Soc:391Google Scholar
  6. 6.
    Colinge J, Gao M, Romano-Rodriguez A, Maes H, Claeys C (1990) Silicon-on-insulator gate-all-around device. IEEE IEDM Tech Dig:595–598Google Scholar
  7. 7.
    Current MI, Pramanik D (1984) MeV implant for silicon device fabrication. Solid State Technol 27:211–216Google Scholar
  8. 8.
    Zhang S, Han R, Lin X, Wu X, Chan M (2004) A stacked CMOS technology on SOI substrate. IEEE Electron Device Lett 25:661–663CrossRefGoogle Scholar
  9. 9.
    Lin X, Zhang S, Wu X, Chan M (2006) Local clustering 3-D stacked CMOS technology for interconnect loading reduction. IEEE Trans on Electron Devices 53:1405–1410CrossRefGoogle Scholar
  10. 10.
    Hisamoto D, Lee WC, Kedzierski J, Takeuchi H, Asano K, Kuo C, Anderson E, King TJ, Bokor J, Hu C (2000) FinFET – A self-aligned double-gate MOSFET scalable to 20 nm. IEEE Trans Electron Device 47:2320–2325CrossRefGoogle Scholar
  11. 11.
    Wu X, Chan PCH, Zhang S, Feng C, Chan M (2005) Stacked 3-D fin-CMOS technology. IEEE Electron Device Lett 26:416–418CrossRefGoogle Scholar
  12. 12.
    Wu X, Chan PCH, Zhang S, Ceng C, Chan M (2005) A three-dimensional stacked fin-CMOS technology for high-density ULSI circuits. IEEE Trans Electron Devices 52:1998–2003CrossRefGoogle Scholar
  13. 13.
    Nowak EJ, Rainey BA, Fried DM, Kedzierski J, Ieong M, Leipold W, Wrignt J, Breitwisch M (1990) A functional FinFET-DGCMOS SRAM cell. IEEE IEDM Tech Dig:411–414Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • Mansun Chan
    • 1
  1. 1.Hong Kong University of Science and TechnologyHong Kong

Personalised recommendations