Thermal Challenges of 3D ICs

  • Sheng-Chih Lin
  • Kaustav Banerjee
Part of the Integrated Circuits and Systems book series (ICIR)


During the past few decades, complementary metal-oxide semiconductor (CMOS) technology scaling along Moore’s law has been the classical solution for the semiconductor industry to meet the ever-increasing demand for lower cost and higher performance [1, 2, 3, 4]. However, in the nanometer regime, the pace of the transistor scaling has been slowing down due to the challenges and hindrances of severe short-channel effects, increasing variability, and power/thermal problems [5, 6, 7]. Also, due to the increase of functionality (transistor counts) of a planar (single active-layer) integrated circuit (IC), the complexity of interconnecting the devices increases dramatically and requires a large number of metal layers. Consequently, performance improvement from transistor scaling cannot be fully exploited and has gradually been constrained by interconnects [8].

Under this scenario, three-dimensional (3D) integration has been proposed as a promising technology to overcome the...


Active Layer Power Dissipation Leakage Power Thermal Interface Material Alternate Direction Implicit Method 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • Sheng-Chih Lin
    • 1
  • Kaustav Banerjee
  1. 1.University of CaliforniaSanta BarbaraUSA

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