Thermal Challenges of 3D ICs

  • Sheng-Chih Lin
  • Kaustav Banerjee
Part of the Integrated Circuits and Systems book series (ICIR)


Active Layer Power Dissipation Leakage Power Thermal Interface Material Alternate Direction Implicit Method 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    Moore GE (1965) Cramming more components onto integrated circuits. Electronics 114–117Google Scholar
  2. 2.
    Moore GE (1975) Progress in digital integrated electronics. IEEE International Electron Devices Meeting, pp 11–13Google Scholar
  3. 3.
    Dennard RH, Gaensslen FH, Rideout VL, Bassous E, LeBlanc AR (1974) Design of ion-implanted MOSFETs with very small physical dimensions. IEEE J Solid-State Circuits 9: 256–268CrossRefGoogle Scholar
  4. 4.
    International Technology Roadmap for Semiconductors (ITRS),
  5. 5.
    Borkar S (1999) Design challenges of technology scaling. IEEE Micro, 19:23–29CrossRefGoogle Scholar
  6. 6.
    De V, Borkar S (1999) Technology and design challenges for low power and high performance. IEEE International Symposium on Low Power Electronics and Design, pp 163–1681Google Scholar
  7. 7.
    Gelsinger PP (2001) Microprocessors for the new millennium: Challenges, opportunities, and New Frontiers. IEEE International Solid-State Circuits Conference, pp 22–25Google Scholar
  8. 8.
    Meindl JD (2003) Beyond Moore's law: The interconnect era. Comput Sci Eng, 5:20–24Google Scholar
  9. 9.
    Banerjee K et al (2001) 3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. Proceedings of the IEEE, vol 89: pp 602– 633CrossRefGoogle Scholar
  10. 10.
    Topol W et al (2006) Three-dimensional integrated circuits. IBM J Res Dev, 50:491–506CrossRefGoogle Scholar
  11. 11.
    Rahman A, Reif R (2000) System-level performance evaluation of three-dimensional integrated circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol 8. pp 671–678CrossRefGoogle Scholar
  12. 12.
    Loi GL, Agrawal B, Srivastava N, Lin S-C, Sherwood T, Banerjee K (2006) A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy. ACM Design Automation Conference, pp 991–996Google Scholar
  13. 13.
    Im S, Banerjee K (2000) Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs. IEEE International Electron Devices Meeting, pp 727–730Google Scholar
  14. 14.
    Kleiner MB, Kühn SA, Ramm P, Weber W (1995) Thermal analysis of vertically integrated circuits. IEEE International Electron Devices Meeting, pp 487–490Google Scholar
  15. 15.
    Rahman A, Reif R (2001) Thermal analysis of three-dimensional (3-D) integrated circuits (ICs), IEEE Interconnect Technology Conference, pp 157–159Google Scholar
  16. 16.
    Banerjee K, Amerasekera A, Dixit G, Hu C (1996) The effect of interconnect scaling and low-k dielectric on the thermal characteristics of the IC metal. IEEE International Electron Devices Meeting, pp 65–68Google Scholar
  17. 17.
    Hamann HF, Weger A, Lacey JA, Cohen E, Atherton C (2006) Power distribution measurements of the dual core powerPC™ 970 MP microprocessor. IEEE International Solid-State Circuits Conference, pp 2172–2179Google Scholar
  18. 18.
    Hamann HF, Weger A, Lacey JA, Hu Z, Bose P, Cohen PE, Wakil J (2007) Hotspot-limited microprocessors: direct temperature and power distribution measurements. IEEE J Solid-State Circuits 42:56–65CrossRefGoogle Scholar
  19. 19.
    Tadayon P (2000) Thermal challenges during microprocessor testing, Intel Technology Journal 3rd quarterGoogle Scholar
  20. 20.
    Viswanath R, Wakharkar V, Watwe A, Lebonheur V (2000) Thermal performance challenges from silicon to system. Intel Technology Journal 3rd quarterGoogle Scholar
  21. 21.
    Prasher RS, Chang JY, Sauciuc I, Narasimhan S, Chau D, Chrysler G, Myers A, Prstic S, Hu C (2005) Nano and micro technology-based next-generation package-level cooling solutions, Intel Technology Journal 4th quarterGoogle Scholar
  22. 22.
    Banerjee K, Mehrotra A (2001) Global (interconnect) warming, IEEE Circuits Devices Mag, 17:16–32Google Scholar
  23. 23.
    Banerjee K, Lin S-C, Keshavarzi A, Narendra S, De V (2003) A self-consistent junction temperature estimation methodology for nanometer scale ICs with implications for performance and thermal management. IEEE International Electron Devices Meeting, pp 887–890Google Scholar
  24. 24.
    Chatterjee A, Nandakumar M, Chen IC (1996) An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuits. IEEE International Symposium on Low Power Electronics and Design, pp 145–150Google Scholar
  25. 25.
    Banerjee K, Mehrotra A (2002) A power-optimal repeater insertion methodology for global interconnects in nanometer designs. IEEE Trans Electron Devices 49:2001–2007CrossRefGoogle Scholar
  26. 26.
    Zeitzoff PM (2004) MOSFET scaling trends and challenges through the end of the roadmap. Custom Integrated Circuits Conference, pp 233–240Google Scholar
  27. 27.
    Lin Y-S, Wu C-C, Chang C-S, Yang R-P, Chen W-M, Liaw J-J, Diaz CH (2002) Leakage scaling in deep submicron CMOS for SoC, IEEE Trans Electron Devices 49:1034–1041CrossRefGoogle Scholar
  28. 28.
    Lin S-C, Chrysler G, Mahajan R, De V, Banerjee K (2007) A self-consistent substrate thermal profile estimation technique for nanoscale ICs – Part I: electrothermal couplings and full-chip package thermal model, IEEE Trans Electron Devices 54(12):3342–3350CrossRefGoogle Scholar
  29. 29.
    Taur T, Ning TH (1998) Fundamentals of modern VLSI devices, Cambridge Univ. PressGoogle Scholar
  30. 30.
    Gelsinger P (2004) Gigascale integration for teraops performance–challenges, Opportunities, and New Frontiers, 41st DAC Keynote.Google Scholar
  31. 31.
    Borkar S, Karnik T, Narendra S, Tschanz J, Keshavarzi A, De V (2003) Parameter variations and impact on circuits and microarchitecture. Design Automation Conference pp 338–342Google Scholar
  32. 32.
    Adam J, Chang C-S, Stankus JJ, Iyer MK, Chen WT (2002) Addressing packaging challenges, IEEE Circuits Devices Mag 18:40–49CrossRefGoogle Scholar
  33. 33.
    Mahajan R, Nair R, Wakharkar V, Swan J, Tang J, Vandentop G (2002) Emerging directions for packaging technologies, Intel Technology Journal 2 nd quarterGoogle Scholar
  34. 34.
    Im S, Srivastava N, Banerjee K, Goodson KE (2005) Scaling analysis of multilevel interconnect temperatures for high performance ICs. IEEE Trans Electron Devices 52:2710–2719CrossRefGoogle Scholar
  35. 35.
    Cess RD (1961) The effect of radiation upon forced-convection heat transfer. Appl Sci Res 10:430–438MATHCrossRefGoogle Scholar
  36. 36.
    Özişik MN (2002) Boundary value problems of heat conduction. Dover PublicationsGoogle Scholar
  37. 37.
    Haberman R (1983) Elementary applied partial differential equations with fourier series and boundary value problems, Prentice Hall.Google Scholar
  38. 38.
    Peaceman DW, Rachford HH (1955) The numerical solution of parabolic and elliptic differential equations. J Soc Ind Appl Math: 28–41Google Scholar
  39. 39.
    Douglas J, Rachford HH (1956) On the numerical solution of heat conduction problems in two or three space variables, Trans Am Math Soc 421–439Google Scholar
  40. 40.
    S-C. Lin, Chrysler G, Mahajan R, De V, Banerjee K (2007) A self-consistent substrate thermal profile estimation technique for nanoscale ICs – Part II: Implementation and implications for power estimation and thermal management, IEEE Trans Electron Devices 54:3351–3360CrossRefGoogle Scholar
  41. 41.
  42. 42.
    Davis WR, Wilson J, Mick S, Xu J, Hua H, Mineo C, Sule AM, Steer M, Franzon PD (2005) Demystifying 3D ICs: the pros and cons of going vertical, IEEE Design & Test of Comput, 22:498–510CrossRefGoogle Scholar
  43. 43.
    Zeng A, Lü J, Rose K, Gutmann RJ (2005) First-order performance prediction of cache memory with wafer-level 3D integration, IEEE Design & Test of Comput 22:548–555CrossRefGoogle Scholar
  44. 44.
    Kühn SA, Kleiner MB, Ramm P, Weber W (1996) Performance modeling of the interconnect structure of a three-dimensional integrated RISC processor/cache system, IEEE Transactions on Components, Packaging, and Manufacturing Technology-Part B, vol 19. pp 719–727CrossRefGoogle Scholar
  45. 45.
    Wong HSP, Frank DJ, Solomon PM, Wann CHJ, Welser JJ (1999) Nanoscale CMOS, Proceedings of the IEEE, vol. 87. pp 537–570Google Scholar
  46. 46.
    De I, Osburn CM (1999) Impact of super-steep-retrograde channel doping profiles on the performance of scaled devices. IEEE Trans Elect Devices 46:1711–1717CrossRefGoogle Scholar
  47. 47.
    Codella CF, Ogura S (1985) Halo doping effects in submicron DI-LDD device design. IEEE International Electron Devices Meeting, pp 230–233Google Scholar
  48. 48.
    Shahidi GG, Warnock J, Fischer S, McFarland PA, Acovic A, Subbanna S, Ganin E, Crabbe E, Comfort J, Sun Y-C, Ning TH, Davari B (1993) High-performance devices for a 0.15-μm CMOS technology, IEEE Electron Device Lett 14:466–468CrossRefGoogle Scholar
  49. 49.
    Su L, Subbanna S, Crabbe E, Agnello P, Nowak E, Schulz R, Rauch S, Ng H, Newman T, Ray A, Hargrove M, Acovic A, Snare J, Crowder S, Chen B, Sun J, Davari B (1996) A high-performance 0.08-μm CMOS. IEEE Symposium on VLSI Technology, pp 12–13Google Scholar
  50. 50.
    Lo SH, Buchanan DA, Taur Y, Wang W (1997) Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFETs, IEEE Electron Device Lett 18:209–211CrossRefGoogle Scholar
  51. 51.
    Chau R, Brask J, Datta S, Dewey G, Doczy M, Doyle B, Kavalieros J, Jin B, Metz M, Majumdar A, Radosavljevic M (2005) Application of high-κ gate dielectrics and metal gate electrodes to enable silicon and non-Silicon logic nanotechnology. Microelectron Eng 80:1–6CrossRefGoogle Scholar
  52. 52.
    Gusev EP, Narayanan V, Frank MM (2006) Advanced high-κ dielectric stacks with polySi and metal gates: recent progress and current challenges. IBM J Res Dev 50:387–410CrossRefGoogle Scholar
  53. 53.
    Tschanz JW, Narendra S, Nair R, De V (2003) Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors. IEEE J Solid-State Circuits 38:826–829CrossRefGoogle Scholar
  54. 54.
    Pedram M, Rabaey J (2002) Power aware design methodologies, Kluwer.Google Scholar
  55. 55.
    Mutoh S, Douseki T, Matsuya Y, Aoki T, Shigematsu S, Yamada J (1995) 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS. IEEE J Solid-State Circuits 30:847–854CrossRefGoogle Scholar
  56. 56.
    Chao KY, Wong DF (1995) Thermal placement for high-performance multichip modules. International Conference on Computer Design, pp 218–223Google Scholar
  57. 57.
    Tsai CH, Kang SM (2000) Cell-level placement for improving substrate thermal distribution. IEEE Transactions on Computer- Aided Design 19:253–266CrossRefGoogle Scholar
  58. 58.
    Goplen B, Sapatnekar S (2003) Efficient thermal placement of standard cells in 3D ICs using a force directed approach. International Conference on Computer Aided Design, pp 86–89Google Scholar
  59. 59.
    Chandrakasan AP, Sheng S, Brodersen RW (1992) Low-power CMOS digital design. IEEE J Solid-State Circuits 27:474–484CrossRefGoogle Scholar
  60. 60.
    Lin S-C, Banerjee K (2008) Cool Chips: Opportunities and Implications for Power and Thermal Management, IEEE Trans Electron Devices 55:245–255Google Scholar
  61. 61.
    Goplen B, Sapatnekar S (2007) Placement of 3D ICs with thermal and interlayer via considerations, ACM Design Automation Conference, pp 626–631Google Scholar
  62. 62.
    Srivastava N, Joshi RV, Banerjee K (2005) Carbon nanotube interconnects: implications for performance, power dissipation and thermal management, IEEE International Electron Devices Meeting, pp 257–260Google Scholar
  63. 63.
    Iwai T, Shioya H, Kondo D, Hirose S, Kawabata A, Sato S, Nihei M, Kikkawa T, Joshin K, Awano Y, Yokoyama N (2005) Thermal and source bumps utilizing carbon nanotubes for flip-chip high power amplifiers. IEEE International Electron Devices Meeting, pp 257–260Google Scholar
  64. 64.
    Xu J, Fisher TS (2006) Enhancement of thermal interface materials with carbon nanotube arrays. Int J Heat and Mass Transf 49:1658–1666CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • Sheng-Chih Lin
    • 1
  • Kaustav Banerjee
  1. 1.University of CaliforniaSanta BarbaraUSA

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