Advertisement

Direct Hybrid Bonding

  • Bart Swinnen
  • Anne Jourdain
  • Piet De Moor
  • Eric Beyne
Chapter
Part of the Integrated Circuits and Systems book series (ICIR)

Introduction

The production of nonmonolithic three-dimensional (3D) systems by stacking components and interconnecting them by through-substrate vias (TSVs) is intrinsically limited to the stacking of “thin” dies. The restriction not only stems from the desire to shrink system height, it also is imposed by the limited capabilities of TSV processing. Most often the metallization process is limiting the aspect ratio (i.e., height/diameter) of the 3D via thus restricting the thickness of the TSV dies. Depending on the type of TSV technology employed, the final wafer or die thickness typically ranges from 100 μm down to 15 μm. Since dies or wafers of such thickness no longer are rigid, it is a requirement that the bond guarantees mechanical stability to the thin stacked die or wafer.

Pure dielectric bonding guarantees such stability simply by the fact that the thin die or wafer is bonded over its entire surface. This method, however, limits the options for electrical interconnection to a...

Keywords

Bonding Process Alignment Accuracy Protrusion Height Electrical Interconnection Hybrid Bonding 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    Beyne E (2001) Technologies for very high bandwidth electrical interconnects between next generation VLSI circuits. In: International Electron Devices Meeting Technical Digest, IEEE, pp 371–374Google Scholar
  2. 2.
    Beyne E (2004) 3D Interconnection and packaging: impending reality or still a dream. In: Proceedings of the 2004 IEEE International Solid State Circuit Conference, IEEE, pp 138–145Google Scholar
  3. 3.
    McMahon JJ, Lu JQ, Gutmann RJ (2005) Wafer bonding of Damascene-Patterned metal/adhesive redistribution layers for via-first three-dimensional (3D) interconnect. In: Proceeding of the 55th Electronic Components and Technology conference, IEEE, pp 331–336Google Scholar
  4. 4.
    Jourdain A, Stoukatch S, De Moor P, Ruythooren W, Pargfrieder S, Swinnen B, Beyne E (2007) Simultaneous Cu–Cu and compliant dielectric bonding for 3D stacking of ICs. In: Proceedings of the International Interconnect Technology Conference, IEEE, pp 207–209Google Scholar
  5. 5.
    Beyne E (2006) The rise of the 3rd dimension for system integration. In: Proceedings of the International Interconnect Technology Conference, IEEE, pp 1–5Google Scholar
  6. 6.
    Swinnen B, Ruythooren W, De Moor P, Bogaerts L, Carbonell L, De Munck K, Eyckens B, Stoukatch S, Sabuncuoglu Tezcan D, Tőkei Z, Vaes J, Van Aelst J, Beyne E (2006) 3D integration by Cu–Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias. In: International Electron Devices Meeting Technical Digest, IEEE, pp 371–374Google Scholar
  7. 7.
  8. 8.
    Jourdain A, Rottenberg X, Carchon G, Tilmans HAC, (2003) Optimization of 0-level packaging for RF-MEMS devices. In: Proceedings Transducers, 2003, Boston, pp 1915–1918Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • Bart Swinnen
    • 1
  • Anne Jourdain
  • Piet De Moor
  • Eric Beyne
  1. 1.IMECB-3001 Leuven

Personalised recommendations