Overview of Wafer-Level 3D ICs

  • Chuan Seng Tan
  • Ronald J. Gutmann
  • L. Rafael Reif
Part of the Integrated Circuits and Systems book series (ICIR)

Background and Introduction

Over the past 40 years, higher computing power was achieved primarily through commensurate performance enhancement of transistors by continuously scaling down the device dimensions as described by Moore’s Law. Integrated circuits (ICs) have essentially remained a planar platform throughout this period of rigorous scaling. As performance enhancement through device scaling becomes more challenging and demand for higher functionality increases, there is tremendous potential to explore the third dimension, i.e., the vertical dimension of ICs. This was rightly envisioned and pointed out by Richard Fenyman, physicist and Nobel Laureate, when he delivered a talk on “Computing Machines in the Future” in Japan in 1985; his original text reads: “Another direction of improvement (of computing power) is to make physical machines three dimensional instead of all on a surface of a chip. That can be done in stages instead of all at once – you can have several layers and...


Active Layer Device Layer Wafer Bonding Static Random Access Memory CMOS Inverter 
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Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • Chuan Seng Tan
    • 1
  • Ronald J. Gutmann
  • L. Rafael Reif
  1. 1.Nanyang Technological UniversitySingapore

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