Advertisement

Overview of Wafer-Level 3D ICs

  • Chuan Seng Tan
  • Ronald J. Gutmann
  • L. Rafael Reif
Chapter
Part of the Integrated Circuits and Systems book series (ICIR)

Background and Introduction

Over the past 40 years, higher computing power was achieved primarily through commensurate performance enhancement of transistors by continuously scaling down the device dimensions as described by Moore’s Law. Integrated circuits (ICs) have essentially remained a planar platform throughout this period of rigorous scaling. As performance enhancement through device scaling becomes more challenging and demand for higher functionality increases, there is tremendous potential to explore the third dimension, i.e., the vertical dimension of ICs. This was rightly envisioned and pointed out by Richard Fenyman, physicist and Nobel Laureate, when he delivered a talk on “Computing Machines in the Future” in Japan in 1985; his original text reads: “Another direction of improvement (of computing power) is to make physical machines three dimensional instead of all on a surface of a chip. That can be done in stages instead of all at once – you can have several layers and...

Keywords

Active Layer Device Layer Wafer Bonding Static Random Access Memory CMOS Inverter 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    Feynman RP (2000) The pleasure of finding things out. Perseus Publishing, Cambridge, p 28Google Scholar
  2. 2.
    Sylvester D, Hu C (2001) Analytical modeling and characterization of deep-submicrometer interconnect. Proc IEEE 89(5):634–664CrossRefGoogle Scholar
  3. 3.
    Kapur P, McVittie JP, Saraswat KC (2001) Realistic copper interconnect performance with technological constraints. In: Proceedings of the IEEE Interconnect Technology Conference, pp 233–235Google Scholar
  4. 4.
    Banerjee K, Souri SJ, Kapur P, Saraswat KC (2001) 3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. Proc IEEE 89(5):602–633CrossRefGoogle Scholar
  5. 5.
    Semiconductor Industry Association (2001) International Technology Roadmap for SemiconductorsGoogle Scholar
  6. 6.
    Su DK, Loinaz MJ, Masui S, Wooley BA (1993) Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits. IEEE J. Solid State Circuits 28(4):420–430CrossRefGoogle Scholar
  7. 7.
    Hwang CG (2006) New paradigms in the silicon industry. In: Keynote Speech, IEDMGoogle Scholar
  8. 8.
    Yang HS, et al. (2004) Dual stress liner for high performance sub-45 nm gate length SOI CMOS manufacturing. In: IEDM Technical Digest, pp 1075–1077Google Scholar
  9. 9.
    Yang M et al (2003) High performance CMOS fabricated on hybrid substrate with different crystal orientations. In: IEDM Technical Digest, pp 453–456Google Scholar
  10. 10.
    Kawamura S, Sasaki N, Iwai T, Nakano M, Takagi M (1983) Three-dimensional CMOS ICs fabricated by using beal recrystallization. IEEE Electron Device Lett 4(10):366–368CrossRefGoogle Scholar
  11. 11.
    Kunio T, Oyama K, Hayashi Y, Morimoto M (1989) Three dimensional ICs, having four stacked active device layers. In: IEDM Technical Digest, pp 837–840Google Scholar
  12. 12.
    Subramanian V, Toita M, Ibrahim NR, Souri SJ, Saraswat KC (1999) Low-leakage germanium-seeded laterally-crystallized single-grain 100-nm TFTs for vertical integration applications. IEEE Electron Device Lett 20(7):341–343CrossRefGoogle Scholar
  13. 13.
    Chan VWC, Chan PCH, Chan M (2001) Three-dimensional CMOS SOI integrated circuit using high-temperature metal-induced lateral crystallization. IEEE Trans Electron Devices 48(7):1394–1399CrossRefGoogle Scholar
  14. 14.
    Pae S, Su T, Denton JP, Neudeck GW (1999) Multiple layers of silicon-on-insulator islands fabrication by selective epitaxial growth. IEEE Electron Device Lett 20(5):194–196CrossRefGoogle Scholar
  15. 15.
    Rajendran B, Shenoy RS, Witte DJ, Chokshi NS, DeLeon RL, Tompa GS, Pease RFW (2007) Low temperature budget processing for sequential 3-D IC fabircation. IEEE Trans Electron Devices 54(4):707–714CrossRefGoogle Scholar
  16. 16.
    Lu J-Q, McMahon JJ, Gutmann RJ (2006) Via-first inter-wafer vertical interconnects utilizing wafer-bonding of damascene-patterned metal/adhesive redistribution layers. In: 3D Packaging Workshop at IMAPS Device Packaging Conference, Scottdale, AZGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • Chuan Seng Tan
    • 1
  • Ronald J. Gutmann
  • L. Rafael Reif
  1. 1.Nanyang Technological UniversitySingapore

Personalised recommendations