Advanced OOP and Testbench Guidelines

Abstract

How would you create a complex class for a bus transaction that also performs error injection and has variable delays? The first approach is to put everything in a large, flat class. This approach is simple to build and easy to understand (all the code is right there in one class), but can be slow to develop and debug. Additionally, such a large class is a maintenance burden, as anyone who wants to make a new transaction behavior has to edit the same file. Just as you would never create a complex RTL design using just one Verilog module, you should break classes down into smaller, reusable blocks.