Design methodology

This chapter summarizes the design procedure developed in Chapters 5 through 7, and exempliffed in detail in Chapter 9.

Implications for design and simulation

This section discusses the result expressed in equations 7.143 through 7.146, which provide several benefits to the design process for low jitter ring oscillators.

Ring jitter dependence on circuit design values.

The most important contribution of 7.143 through 7.146 is to relate circuit design parameters - component values and currents - to the figure of merit K. Through the time/frequency technique in Chapter 5, the end user's figure of merit σ_x can be expressed as a function of K and the loop bandwidth. Thus we can complete the link in the design process from the component values that we choose in circuit-level design, to the closed loop jitter measured by the end user at the system level.

Fundamental limits of jitter

The equations provide a simple, direct means of relating jitter performance to fundamental design parameters such as power dissipation and waveform amplitude.

For example, 7.143 and 7.144 indicate a direct link between DC power dissipation and jitter. Thus if we are designing in a low power application, we can immediately determine the best possible jitter that could be achieved at a given power dissipation.

As another example, 7.143 through 7.146 show that there is a link between waveform amplitude (V _SWINGS or _VDD ) and jitter as characterized by K. Thus if we are designing in a low voltage application with little headroom for large signal swings, we can immediately determine the best possible jitter that could be achieved at a given signal amplitude.