Sources of jitter in ring oscillators
In this chapter we will consider application of the jitter analysis method developed in Chapter 6 to circuit-level sources of jitter. The goal is to develop simple analytic expression relating system level performance as described by Kto circuit-level design decisions such as device sizes, resistance and capacitance values, and bias currents.
Section 7.1 presents a framework for classifying the effects of circuit-level noise sources on oscillator jitter. Four general ways in which noise sources can affect gate delay are enumerated, and detailed descriptions are developed in sections 7.2 through 7.5. Experimental verification is presented in section 7.7, and section 7.9 presents a comparison with results of a similar analysis on harmonic (LC) oscillators.
KeywordsNoise Source Voltage Noise Ring Oscillator Switching Element Element Noise
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