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Hybrid Semiconductor-Molecular Integrated Circuits for Digital Electronics: CMOL Approach

  • Dmitri B. Strukov
Part of the Nanostructure Science and Technology book series (NST)

Abstract

This chapter describes architectures of digital circuits including memories, general-purpose, and application-specific reconfigurable Boolean logic circuits for the prospective hybrid CMOS/nanowire/nanodevice (“CMOL”) technology. The basic idea of CMOL circuits is to combine the advantages of CMOS technology (including its flexibility and high fabrication yield) with those of molecular-scale nanodevices. Two-terminal nanodevices would be naturally incorporated into nanowire crossbar fabric, enabling very high function density at acceptable fabrication costs. In order to overcome the CMOS/nanodevice interface problem, in CMOL circuits the interface is provided by sharp-tipped pins that are distributed all over the circuit area, on top of the CMOS stack. We show that CMOL memories with a nano/CMOS pitch ratio close to 10 may be far superior to the densest semiconductor memories by providing, e.g., 1 Tbit/cm\(^2\) density even for the plausible defect fraction of 2%. Even greater defect tolerance (more than 20% for 99% circuit yield) can be achieved in both types of programmable Boolean logic CMOL circuits. In such circuits, two-terminal nanodevices provide programmable diode functionality for logic circuit operation, and allow circuit mapping and reconfiguration around defective nanodevices, while CMOS subsystem is used for signal restoration and latching. Using custom-developed design automation tools we have successfully mapped on reconfigurable general-purpose logic fabric (“CMOL FPGA”) the well-known Toronto 20 benchmark circuits and estimated their performance. The results have shown that, in addition to high defect tolerance, CMOL FPGA circuits may have extremely high density (more than two orders of magnitude higher that that of usual CMOS FPGA with the same CMOS design rules) while operating at higher speed at acceptable power consumption. Finally, our estimates indicate that reconfigurable application-specific (“CMOL DSP”) circuits may increase the speed of low-level image processing tasks by more than two orders of magnitude as compared to the fastest CMOS DSP chips implemented with the same CMOS design rules at the same area and power consumption.

Keywords

Defect Tolerance Logic Circuit Memory Array Benchmark Circuit Relay Cell 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgments

The author is especially grateful to K. K. Likharev who equally contributed to the results presented in this chapter. Also, useful discussions of various aspects of digital CMOL circuits with J. Barhen, V. Beiu, R. Brayton, S. Chatterjee, S. Das, A. DeHon, D. Hammerstrom, A. Korkin, P. Kuekes, J. Lukens, A. Mayr, A. Mishchenko, N. Quitoriano, G. Snider, M. Stan, D. Stewart, N. H. Di Spigna, R. S. Williams, T. Zhang, and N. Zhitenev are gratefully acknowledged. The work has been supported in part by AFOSR, DTO, and NSF.

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Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • Dmitri B. Strukov
    • 1
  1. 1.Hewlett-Packard LaboratoriesPalo AltoUSA

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