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Hybrid Semiconductor-Molecular Integrated Circuits for Digital Electronics: CMOL Approach

  • Chapter
Nanoelectronics and Photonics

Part of the book series: Nanostructure Science and Technology ((NST))

Abstract

This chapter describes architectures of digital circuits including memories, general-purpose, and application-specific reconfigurable Boolean logic circuits for the prospective hybrid CMOS/nanowire/nanodevice (“CMOL”) technology. The basic idea of CMOL circuits is to combine the advantages of CMOS technology (including its flexibility and high fabrication yield) with those of molecular-scale nanodevices. Two-terminal nanodevices would be naturally incorporated into nanowire crossbar fabric, enabling very high function density at acceptable fabrication costs. In order to overcome the CMOS/nanodevice interface problem, in CMOL circuits the interface is provided by sharp-tipped pins that are distributed all over the circuit area, on top of the CMOS stack. We show that CMOL memories with a nano/CMOS pitch ratio close to 10 may be far superior to the densest semiconductor memories by providing, e.g., 1 Tbit/cm\(^2\) density even for the plausible defect fraction of 2%. Even greater defect tolerance (more than 20% for 99% circuit yield) can be achieved in both types of programmable Boolean logic CMOL circuits. In such circuits, two-terminal nanodevices provide programmable diode functionality for logic circuit operation, and allow circuit mapping and reconfiguration around defective nanodevices, while CMOS subsystem is used for signal restoration and latching. Using custom-developed design automation tools we have successfully mapped on reconfigurable general-purpose logic fabric (“CMOL FPGA”) the well-known Toronto 20 benchmark circuits and estimated their performance. The results have shown that, in addition to high defect tolerance, CMOL FPGA circuits may have extremely high density (more than two orders of magnitude higher that that of usual CMOS FPGA with the same CMOS design rules) while operating at higher speed at acceptable power consumption. Finally, our estimates indicate that reconfigurable application-specific (“CMOL DSP”) circuits may increase the speed of low-level image processing tasks by more than two orders of magnitude as compared to the fastest CMOS DSP chips implemented with the same CMOS design rules at the same area and power consumption.

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Notes

  1. 1.

    For example, for the most prospective ballistic field-effect transistors, this is mainly due to leakage tunneling of thermally excited electrons. In single-electron transistors, the gain is limited by island to gate capacitance ratio. The gain of interference transistors is also typically small, see, e.g., Ref. [10].

  2. 2.

    As it will be shown later in this work, the diode-like characteristic is necessary for the operation of the hybrid memory circuits and is helpful for the proposed logic circuits. However, simple programmable resistance switches (Fig. 4.1b) could be enough for, e.g., nanoelectronic neuromorphic networks [38, 39, 40, 41], programmable interconnect hybrid CMOS/nanodevice architectures [42, 43], as well as Goto-pair-based circuit architectures [22, 44, 45]. The latter two concepts will be briefly discussed below.

  3. 3.

    For more extensive review of thin-film devices, see, e.g., Refs. [47, 48, 49, 50, 51].

  4. 4.

    Another, not less exciting, application of the crossbar nanoelectronic hybrids, neuromorphic networks [38, 39, 40, 41], is out of the scope of this work.

  5. 5.

    Here, we do not include in our comparison the data storage systems (such as hard disk drives) which cannot be used for bit-addressable memories because of their very large (millisecond-scale) access time.

  6. 6.

    Actually, only one of the “write 0” and “write 1” operations can be performed simultaneously with all cells. Because of the opposite polarity of the necessary voltages across nanodevices for these two operations, the complete write may be implemented in two steps, e.g., first writing 0s and then writing 1s.

  7. 7.

    We have only considered “stuck-on-open” kind of defects in this work. It is worth mentioning that considered architecture is very efficient for tolerating all other types of defects (e.g., broken or shorted nanowires), except for “stuck-on-close” (permanently shortened) nanodevices.

  8. 8.

    Though formally the results depend on the total memory size \(N\) and yield \(Y\), they are rather insensitive to these parameters in the range of our interest (\(N \approx 10^{12}\) bits, \(Y\approx90\)%). As Fig. 4.13 shows, the required memory access time \(\tau\) also has a marginal effect on density, provided \(\tau\) is not too small.

  9. 9.

    In principle, this problem can be alleviated by making the width of nanowires in one dimension comparable with that of lithographically defined wires [35]. However, that also means that such hybrid circuits cannot take full advantage (only in one dimension) of nanodevice nanometer-scale footprints.

  10. 10.

    As a reminder, in all discussed crossbar circuits above, as well as in our approach for Boolean logic described in this section and Section 4.6, the state of nanodevices remains unchanged during circuit operation.

  11. 11.

    Note that even though the nanowire crossbar in Ref. [28] was rotated by the additional 45\(^\circ\) angle, which was convenient for manual mapping, it does not affect the performance results.

  12. 12.

    The best performance is achieved if the pin contacts the wire fragment in its middle, and our analysis has been carried out with this assumption. Since lower layer nanowire segments are cut by upper layer pins, a connection exactly in a center is easily achievable, i.e., by locating upper level pins correspondingly. For upper layer pins, a similar trick can be done, if upper layer nanowire breaks are provided by features of the same lithographic mask that defines interface pin positions. Also note that a modest misalignment of the pin and the breaks (by \({\sim}F_{\rm CMOS}\)) reduces the circuit performance only by a small factor of the order of \(1/\boldsymbol{\upeta} \ll1\).

  13. 13.

    It is worth noting that a major advantage of the Cell-type processors for the low-level image processing tasks is a very fast (nanosecond-scale) time necessary for changing the running task (e.g., the filter size). CMOL DSP can almost certainly have a sub-100 μs time of switching from one task to another.

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Acknowledgments

The author is especially grateful to K. K. Likharev who equally contributed to the results presented in this chapter. Also, useful discussions of various aspects of digital CMOL circuits with J. Barhen, V. Beiu, R. Brayton, S. Chatterjee, S. Das, A. DeHon, D. Hammerstrom, A. Korkin, P. Kuekes, J. Lukens, A. Mayr, A. Mishchenko, N. Quitoriano, G. Snider, M. Stan, D. Stewart, N. H. Di Spigna, R. S. Williams, T. Zhang, and N. Zhitenev are gratefully acknowledged. The work has been supported in part by AFOSR, DTO, and NSF.

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  1. Hewlett-Packard Laboratories, 1501 Page Mill Road, Palo Alto, CA 94304, USA

    Dmitri B. Strukov

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  1. Nano and Giga Solutions, Gilbert, AZ, USA

    Anatoli Korkin

  2. Initiative National de la Recherche Scientifique, Énergie, Matériaux et Télécommunications, UniversitÉdu QuÉbec, QuÉbec, QC, Canada

    Federico Rosei

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Strukov, D.B. (2008). Hybrid Semiconductor-Molecular Integrated Circuits for Digital Electronics: CMOL Approach. In: Korkin, A., Rosei, F. (eds) Nanoelectronics and Photonics. Nanostructure Science and Technology. Springer, New York, NY. https://doi.org/10.1007/978-0-387-76499-3_4

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