Hybrid Semiconductor-Molecular Integrated Circuits for Digital Electronics: CMOL Approach

  • Dmitri B. Strukov
Part of the Nanostructure Science and Technology book series (NST)


This chapter describes architectures of digital circuits including memories, general-purpose, and application-specific reconfigurable Boolean logic circuits for the prospective hybrid CMOS/nanowire/nanodevice (“CMOL”) technology. The basic idea of CMOL circuits is to combine the advantages of CMOS technology (including its flexibility and high fabrication yield) with those of molecular-scale nanodevices. Two-terminal nanodevices would be naturally incorporated into nanowire crossbar fabric, enabling very high function density at acceptable fabrication costs. In order to overcome the CMOS/nanodevice interface problem, in CMOL circuits the interface is provided by sharp-tipped pins that are distributed all over the circuit area, on top of the CMOS stack. We show that CMOL memories with a nano/CMOS pitch ratio close to 10 may be far superior to the densest semiconductor memories by providing, e.g., 1 Tbit/cm\(^2\) density even for the plausible defect fraction of 2%. Even greater defect tolerance (more than 20% for 99% circuit yield) can be achieved in both types of programmable Boolean logic CMOL circuits. In such circuits, two-terminal nanodevices provide programmable diode functionality for logic circuit operation, and allow circuit mapping and reconfiguration around defective nanodevices, while CMOS subsystem is used for signal restoration and latching. Using custom-developed design automation tools we have successfully mapped on reconfigurable general-purpose logic fabric (“CMOL FPGA”) the well-known Toronto 20 benchmark circuits and estimated their performance. The results have shown that, in addition to high defect tolerance, CMOL FPGA circuits may have extremely high density (more than two orders of magnitude higher that that of usual CMOS FPGA with the same CMOS design rules) while operating at higher speed at acceptable power consumption. Finally, our estimates indicate that reconfigurable application-specific (“CMOL DSP”) circuits may increase the speed of low-level image processing tasks by more than two orders of magnitude as compared to the fastest CMOS DSP chips implemented with the same CMOS design rules at the same area and power consumption.


Defect Tolerance Logic Circuit Memory Array Benchmark Circuit Relay Cell 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



The author is especially grateful to K. K. Likharev who equally contributed to the results presented in this chapter. Also, useful discussions of various aspects of digital CMOL circuits with J. Barhen, V. Beiu, R. Brayton, S. Chatterjee, S. Das, A. DeHon, D. Hammerstrom, A. Korkin, P. Kuekes, J. Lukens, A. Mayr, A. Mishchenko, N. Quitoriano, G. Snider, M. Stan, D. Stewart, N. H. Di Spigna, R. S. Williams, T. Zhang, and N. Zhitenev are gratefully acknowledged. The work has been supported in part by AFOSR, DTO, and NSF.


  1. 1.
    K. K. Likharev, Electronics below 10 nm, in Nano and Giga Challenges in Microelectronics, pages 27–68, Elsevier, Amsterdam, 2003.Google Scholar
  2. 2.
    D. J. Frank et al., Proc. IEEE 89, 259 (2001).Google Scholar
  3. 3.
    available online at
  4. 4.
    R. Lewis, Practical Digital Image Processing, Ellis Horwood, New York, 1990.Google Scholar
  5. 5.
    P. H. Swain and S. M. Davis, Remote Sensing. The Quantitative Approach, McGraw-Hill, New York, 1978.Google Scholar
  6. 6.
    S. M. Chai et al., Appl. Optics 39, 835 (2000).Google Scholar
  7. 7.
    D. C. Pham et al., IEEE J. Solid-State Circ. 41, 179 (2006).Google Scholar
  8. 8.
    D. B. Strukov and K. K. Likharev, IEEE Tran. Nanotechnol. (2007), accepted for publication.Google Scholar
  9. 9.
    D. B. Strukov and K. K. Likharev, IEEE Tran. Nanotechnol. 6, 696 (2007).Google Scholar
  10. 10.
    C. A. Stafford, D. M. Cardamone, and S. Mazumdar, Nanotechnology 18, 424014 (2007).Google Scholar
  11. 11.
    W. Wang, T. Lee, and M. Reed, Intrinsic electronic conduction mechanisms in self-assembled monolayers, in Introducing Molecular Electronics, edited by G. Cuniberti, G. Fagas, and K. Richter, pages 275–300, Springer, Berlin, 2005.Google Scholar
  12. 12.
    D. Porath, DNA-based devices, in Introducing Molecular Electronics, edited by G. Cuniberti, G. Fagas, and K. Richter, pages 411–446, Springer, Berlin, 2005.Google Scholar
  13. 13.
    S. C. Goldstein and M. Budiu, NanoFabrics: Spatial computing using molecular electronics, in Proc. of ISCA’01, pages 178–189, GÖteborg, Sweden, 2001.Google Scholar
  14. 14.
    M. Masoumi, F. Raissi, M. Ahmadian, and P. Keshavarzi, Nanotechnology 17, 89 (2006).Google Scholar
  15. 15.
    T. Wang, Z. Qi, and C. A. Moritz, Opportunities and challenges in application-tuned circuits and architectures based on nanodevicess, in Proc. of CCF’04, pages 503–511, Italy, 2004.Google Scholar
  16. 16.
    M. M. Ziegler and M. R. Stan, IEEE Trans. Nanotechnol. 2, 217 (2003).Google Scholar
  17. 17.
    A. DeHon, IEEE Trans. Nanotechnol. 2, 23 (2003).Google Scholar
  18. 18.
    A. DeHon, S. C. Goldstein, P. J. Kuekes, and P. Lincoln, IEEE Trans. Nanotechnol. 4, 215 (2005).Google Scholar
  19. 19.
    M. M. Ziegler et al., Molecular Electronics III 1006, 312 (2003).Google Scholar
  20. 20.
    T. Hogg and G. Snider, JETTA 23, 117 (2007).Google Scholar
  21. 21.
    G. Snider, P. Kuekes, T. Hogg, and R. S. Williams, Appl. Phys. A-Mater. Sci. Process. 80, 1183 (2005).Google Scholar
  22. 22.
    G. S. Snider and P. J. Kuekes, IEEE Trans. Nanotechnol. 5, 129 (2006).Google Scholar
  23. 23.
    T. Hogg and G. S. Snider, IEEE Trans. Nanotechnol. 5, 97 (2006).Google Scholar
  24. 24.
    C. Dong, W. Wang, and S. Haruehanroengra, Micro & Nano Lett. 1, 74 (2007).Google Scholar
  25. 25.
    D. Tu, M. Liu, W. Wang, and S. Haruehanroengra, Micro & Nano Lett. 2, 40 (2007).Google Scholar
  26. 26.
    D. B. Strukov and K. K. Likharev, CMOL FPGA circuits, in Proc. of CDES’06, pages 213–219, Las Vegas, NE, 2006.Google Scholar
  27. 27.
    D. B. Strukov and K. K. Likharev, Nanotechnology 16, 137 (2005).Google Scholar
  28. 28.
    D. B. Strukov and K. K. Likharev, Nanotechnology 16, 888 (2005).Google Scholar
  29. 29.
    D. B. Strukov and K. K. Likharev, A reconfigurable architecture for hybrid CMOS/Nanodevice circuits, in Proc. of FPGA’06, pages 131–140, New York, ACM Press, 2006.Google Scholar
  30. 30.
    D. B. Strukov and K. K. Likharev, J. Nanosci. Nanotechnol. 7, 151 (2007).Google Scholar
  31. 31.
    A. DeHon and K. Likharev, Hybrid CMOS/nanoelectronic digital circuits: Devices, architectures, and design automation, in Proc. of ICCAD’05, pages 375–382, 2005.Google Scholar
  32. 32.
    K. K. Likharev and D. B. Strukov, CMOL: Devices, circuits, and architectures, in Introducing Molecular Electronics, edited by G. Cuniberti, G. Fagas, and K. Richter, pages 447–478, Springer, Berlin, 2005.Google Scholar
  33. 33.
    M. R. Stan, P. D. Franzon, S. C. Goldstein, J. C. Lach, and M. M. Ziegler, Proc. IEEE 91, 1940 (2003).Google Scholar
  34. 34.
    P. J. Kuekes, G. S. Snider, and R. S. Williams, Sci. Am. 293, 72 (2005).Google Scholar
  35. 35.
    A. DeHon, ACM J. Emerg. Technol. Comput. Syst. 1, 109 (2005).Google Scholar
  36. 36.
    S. Das, G. Rose, M. M. Ziegler, C. A. Picconatto, and J. E. Ellenbogen, Architecture and simulations for nanoprocessor systems integrated on the molecular scale, in Introducing Molecular Electronics, edited by G. Cuniberti, G. Fagas, and K. Richter, pages 479–515, Springer, Berlin, 2005.Google Scholar
  37. 37.
    K. K. Likharev, Hybrid semiconductor/nanoelectronic circuits, in Proc. of NanoTech’07, pages 552–555, Cambridge, MA, 2007.Google Scholar
  38. 38.
    K. K. Likharev, A. Mayr, I. Muckra, and Ö. Türel, Ann. NY Acad. Sci. 1006, 146 (2003).Google Scholar
  39. 39.
    O. Türel, J. H. Lee, X. L. Ma, and K. K. Likharev, Int. J. Circ. Theory App. 32, 277 (2004).Google Scholar
  40. 40.
    J. H. Lee and K. K. Likharev, Int. J. Circ. Theory App. 35, 239 (2007).Google Scholar
  41. 41.
    G. S. Snider, Nanotechnology 18, 365202 (2007).Google Scholar
  42. 42.
    G. S. Snider and R. S. Williams, Nanotechnology 18, 035204 (2007).Google Scholar
  43. 43.
    A. A. Gayasen, N. Vijaykrishnan, and M. J. Irwin, Exploring technology alternatives for nano-scale FPGA interconnects, in Proc. of DAC’05, pages 921–926, 2005.Google Scholar
  44. 44.
    G. Snider, Appl. Phys. A-Mater. Sci. Process. 80, 1165 (2005).Google Scholar
  45. 45.
    P. J. Kuekes, D. R. Stewart, and R. S. Williams, J. Appl. Phys. 97, 034301 (2005).Google Scholar
  46. 46.
    D. R. Stewart et al., Nano Lett. 4, 133 (2004).Google Scholar
  47. 47.
    G. Dearnaley, A. M. Stoneham, and D. V. Morgan, Reports on Progress in Phys. 33, 1129 (1970).Google Scholar
  48. 48.
    G. Cuniberti, G. Fagas, and K. Richter, editors, Introducing Molecular Electronics, Springer, Berlin, 2005.Google Scholar
  49. 49.
    J. C. Scott and L. D. Bozano, Adv. Mater. 19, 1452 (2007).Google Scholar
  50. 50.
    A. M. Bratkovsky, Current rectification, switching, polarons, and defects in molecular electronics devices, in Polarons in Advanced Materials, edited by A. S. Alexandrov, Canopus/Springer, Bristol, England, 2007.Google Scholar
  51. 51.
    H. Pagnia and N. Sotnik, Phys. Status Solidi A-Appl. Res. 108, 11 (1988).Google Scholar
  52. 52.
    L. P. Ma, S. Pyo, J. Ouyang, Q. F. Xu, and Y. Yang, Appl. Phys. Lett. 82, 1419 (2003).Google Scholar
  53. 53.
    L. D. Bozano, B. W. Kean, V. R. Deline, J. R. Salem, and J. C. Scott, Appl. Phys. Lett. 84, 607 (2004).Google Scholar
  54. 54.
    J. Y. Ouyang, C. W. Chu, C. R. Szmanda, L. P. Ma, and Y. Yang, Nature Mater. 3, 918 (2004).Google Scholar
  55. 55.
    F. Verbakel, S. C. J. Meskers, and R. A. J. Janssen, Appl. Phys. Lett. 89, 102103 (2006).Google Scholar
  56. 56.
    R. Sezi et al., IEDM Tech. Digest, 10.2.1 (2003).Google Scholar
  57. 57.
    L. P. Ma, Q. F. Xu, and Y. Yang, Appl. Phys. Lett. 84, 4908 (2004).Google Scholar
  58. 58.
    Y. S. Lai, C. H. Tu, D. L. kWong, and J. S. Chen, Appl. Phys. Lett. 87, 122101 (2005).Google Scholar
  59. 59.
    Q. X. Lai, Z. H. Zhu, Y. Chen, S. Patil, and F. Wudl, Appl. Phys. Lett. 88, 133515 (2006).Google Scholar
  60. 60.
    J. H. A. Smits, S. C. J. Meskers, R. A. J. Janssen, A. W. Marsman, and D. M. de Leeuw, Adv. Mater. 17, 1169 (2005).Google Scholar
  61. 61.
    C. P. Collier et al., Science 285, 391 (1999).Google Scholar
  62. 62.
    J. H. Krieger, S. V. Trubin, S. B. Vaschenko, and N. F. Yudanov, Synthetic Metals 122, 199 (2001).Google Scholar
  63. 63.
    C. Li et al., App. Phys. Lett. 82, 645 (2003).Google Scholar
  64. 64.
    W. Wu et al., App. Phys. A-Mater. Sci. Process. 80, 1173 (2005).Google Scholar
  65. 65.
    Y.-C. Chen et al., IEDM Tech. Digest, 37.4.1 (2003).Google Scholar
  66. 66.
    M. Kund et al., IEDM Tech. Digest, 31.5 (2005).Google Scholar
  67. 67.
    Z. Wang et al., IEEE Elec. Dev. Lett. 28, 14 (2007).Google Scholar
  68. 68.
    H. B. Chung, K. Shin, and J. M. Lee, J. Vac. Sci. Technol. A 25, 48 (2007).Google Scholar
  69. 69.
    M. H. R. Lankhorst, B. W. S. M. M. Ketelaars, and R. A. M. Wolters, Nature Mater. 4, 347 (2005).Google Scholar
  70. 70.
    M. N. Kozicki, M. Park, and M. Mitkova, IEEE Trans. Nanotechnol. 4, 331 (2005).Google Scholar
  71. 71.
    J. Hu, A. J. Snell, J. Hajto, M. J. Rose, and W. Edmiston, Thin Solid Films 396, 240 (2001).Google Scholar
  72. 72.
    J. M. Shannon, S. P. Lau, A. D. Annis, and B. J. Sealy, Solid-State Electron. 42, 91 (1998).Google Scholar
  73. 73.
    C. A. Richter, D. R. Stewart, D. A. A. Ohlberg, and R. S. Williams, Appl. Phys. A-Mater. Sci. Process. 80, 1355 (2005).Google Scholar
  74. 74.
    J. R. Jameson et al., Appl. Phys. Lett. 91, 112101 (2007).Google Scholar
  75. 75.
    B. J. Choi et al., J. Appl. Phys. 98, 033715 (2005).Google Scholar
  76. 76.
    D. S. Jeong, H. Schroeder, and R. Waser, Electrochem. Solid State Lett. 10, G51 (2007).Google Scholar
  77. 77.
    K. M. Kim, B. J. Choi, Y. C. Shin, S. Choi, and C. S. Hwang, Appl. Phys. Lett. 91, 012907 (2007).Google Scholar
  78. 78.
    H. Sim et al., Microelectron. Eng. 80, 260 (2005).Google Scholar
  79. 79.
    A. Chen et al., IEDM Tech. Digest, 31.3 (2005).Google Scholar
  80. 80.
    D. C. Kim et al., Appl. Phys. Lett. 88, 202102 (2006).Google Scholar
  81. 81.
    H. Shima et al., Appl. Phys. Lett. 91, 012901 (2007).Google Scholar
  82. 82.
    S. Seo et al., Appl. Phys. Lett. 85, 5655 (2004).Google Scholar
  83. 83.
    H. Shima, F. Takano, Y. Tamai, H. Akinaga, and I. H. Inoue, Jap. J. Appl. Phys. 2 46, L57 (2007).Google Scholar
  84. 84.
    G. Stefanovich, A. Pergament, and D. Stefanovich, J. Phys.-Cond. Matter 12, 8837 (2000).Google Scholar
  85. 85.
    B. G. Chae, H. T. Kim, D. H. Youn, and K. Y. Kang, Phys. B-Cond. Matt. 369, 76 (2005).Google Scholar
  86. 86.
    A. Asamitsu, Y. Tomioka, H. Kuwahara, and Y. Tokura, Nature 388, 50 (1997).Google Scholar
  87. 87.
    K. Szot, W. Speier, G. Bihlmayer, and R. Waser, Nature Mater. 5, 312 (2006).Google Scholar
  88. 88.
    D. S. Kim, Y. H. Kim, C. E. Lee, and Y. T. Kim, Phys. Rev. B 74, 174430 (2006).Google Scholar
  89. 89.
    A. Sawa, T. Fujii, M. Kawasaki, and Y. Tokura, Appl. Phys. Lett. 88, 232112 (2006).Google Scholar
  90. 90.
    S. Karg, G. I. Meijer, D. Widmer, and J. G. Bednorz, Appl. Phys. Lett. 89, 072106 (2006).Google Scholar
  91. 91.
    R. Fors, S. I. Khartsev, and A. M. Grishin, Phys. Rev. B 71, (2005).Google Scholar
  92. 92.
    M. Hamaguchi, K. Aoyama, S. Asanuma, Y. Uesu, and T. Katsufuji, Appl. Phys. Lett. 88, 142508 (2006).Google Scholar
  93. 93.
    J. R. Contreras et al., Appl. Phys. Lett. 83, 4595 (2003).Google Scholar
  94. 94.
    P. Levy et al., Phys. Rev. B 65, 140401 (2002).Google Scholar
  95. 95.
    C. N. Lau, D. R. Stewart, R. S. Williams, and M. Bockrath, Nano Lett. 4, 569 (2004).Google Scholar
  96. 96.
    D. S. Jeong, H. Schroeder, and R. Waser, Appl. Phys. Lett. 89, 082909 (2006).Google Scholar
  97. 97.
    J. J. Blackstock et al., APS Meeting Abstracts, 10004 (2006).Google Scholar
  98. 98.
    J. Blanc and D. L. Staebler, Phys. Rev. B 4, 3548 (1971).Google Scholar
  99.  99.
    S. FÖlling, Ö. Türel, and K. K. Likharev, Single-electron latching switches as nanoscale synapses, in Proc. of IJCNN’01, pages 216–221, Mount Royal, New York, Int. Neural Network Soc., 2001.Google Scholar
  100. 100.
    N. B. Zhitenev, H. Meng, and Z. Bao, Phys. Rev. Lett. 88, 226801 (2002).Google Scholar
  101. 101.
    H. B. Akkerman, P. W. M. Blom, D. M. de Leeuw, and B. de Boer, Nature 441, 69 (2006).Google Scholar
  102. 102.
    J. Goldberger, A. I. Hochbaum, R. Fan, and P. D. Yang, Nano Lett. 6, 973 (2006).Google Scholar
  103. 103.
    T. Bryllert, L. E. Wernersson, T. Lowgren, and L. Samuelson, Nanotechnology 17, S227 (2006).Google Scholar
  104. 104.
    C. M. S. Torreset al., vMater. Sci. Eng. C-Biomimetic Supramol. Syst. 23, 23 (2003).Google Scholar
  105. 105.
    L. J. Guo, J. Phys. D-Appl. Phys. 37, R123 (2004).Google Scholar
  106. 106.
    D. J. Wagner and A. H. Jayatissa, Nanoimprint lithography: Review of aspects and applications, in Nanofabrication: Technologies, Devices, and Applications II, edited by W. Y. Lai, L. E. Ocola, and S. Pau, volume 6002, page 60020R, SPIE, 2005.Google Scholar
  107. 107.
    I. W. Hamley, Angewandte Chemie-International Edition 42, 1692 (2003).Google Scholar
  108. 108.
    S. R. J. Brueck, There are no fundamental limits to optical lithography, in International Trends in Applied Optics, pages 85–109, SPIE Press, Bellingham, WA, 2002.Google Scholar
  109. 109.
    H. H. Solak et al., Microelectron. Eng. 67–8, 56 (2003).Google Scholar
  110. 110.
    G.-Y. Jung et al., Nano Lett. 2, 351 (2006).Google Scholar
  111. 111.
    Y. Chen et al., Nanotechnology 14, 462 (2003).Google Scholar
  112. 112.
    F. Sun and T. Zhang, IEEE Trans. Nanotechnol. 6, 341 (2007).Google Scholar
  113. 113.
    G. Snider, P. Kuekes, and R. S. Williams, Nanotechnology 15, 881 (2004).Google Scholar
  114. 114.
    A. DeHon and H. Naeimi, IEEE Des. Test Comput. 22, 306 (2005).Google Scholar
  115. 115.
    J. R. Heath, P. J. Kuekes, G. S. Snider, and R. S. Williams, Science 280, 1716 (1998).Google Scholar
  116. 116.
    J. E. Green et al., Nature 445, 414 (2007).Google Scholar
  117. 117.
    C. J. Amsinck, N. H. Di Spigna, D. P. Nackashi, and P. D. Franzon, Nanotechnology 16, 2251 (2005).Google Scholar
  118. 118.
    A. DeHon, Design of programmable interconnect for sublithographic programmable logic arrays, in Proc. of FPGA’05, pages 127–137, Monterey, CA, 2005.Google Scholar
  119. 119.
    S. C. Goldstein and D. Rosewater, Digital logic using molecular electronics, in Proc. of ISSCC’02, page 12.5, San Francisco, CA, 2002.Google Scholar
  120. 120.
    A. DeHon, P. Lincoln, and J. E. Savage, IEEE Trans. Nanotechnol. 2, 165 (2003).Google Scholar
  121. 121.
    P. J. Kuekes, W. Robinett, G. Seroussi, and R. S. Williams, App. Phys. A-Mater. Sci. Process. 80, 1161 (2005).Google Scholar
  122. 122.
    P. J. Kuekes et al., Nanotechnology 17, 1052 (2006).Google Scholar
  123. 123.
    B. Gojman, E. Rachlin, and J. E. Savage, ACM J. Emerg. Technol. Comput. Syst. 1, 73 (2005).Google Scholar
  124. 124.
    G. F. Cerofolini, Appl. Phys. A-Mater. Sci. Process. 86, 31 (2007).Google Scholar
  125. 125.
    K. K. Likharev, Interface 14, 43 (2005).Google Scholar
  126. 126.
    N. H. Di Spigna, D. P. Nackashi, C. J. Amsinck, S. R. Sonkusale, and P. Franzon, IEEE Trans. Nanotechnol. 5, 356 (2006).Google Scholar
  127. 127.
    R. J. Luyken and F. Hofmann, Nanotechnology 14, 273 (2003).Google Scholar
  128. 128.
    N. E. Gilbert and M. N. Kozicki, IEEE J. Solid-State Circ. 42, 1383 (2007).Google Scholar
  129. 129.
    I. G. Baek et al., IEDM Tech. Digest, 31.4 (2005).Google Scholar
  130. 130.
    P. P. Sotiriais, IEEE Tran. Inf. Theory 52, 3019 (2006).Google Scholar
  131. 131.
    B. Prince, Semiconductor Memories: A Handbook of Design, Manufacture, and Application, Wiley, Chichester, 2nd edition, 1991.Google Scholar
  132. 132.
    K. Chakraborty and P. Mazumder, Fault-Tolerance and Reliability Techniques for High-Density Random-Access Memories, Prentice Hall, Upper Saddle River, NJ, 2002.Google Scholar
  133. 133.
    C. T. Huang, C. F. Wu, J. F. Li, and C. W. Wu, IEEE Trans. Reliab. 52, 386 (2003).Google Scholar
  134. 134.
    C. H. Stapper and H. S. Lee, IEEE Trans. Comput. 41, 1078 (1992).Google Scholar
  135. 135.
    R. E. Blahut, Algebraic Codes for Data Transmission, Cambridge University Press, Cambridge, 2003.Google Scholar
  136. 136.
    J. von Neumann, Probabilistic logics and the synthesis of reliable organisms from unreliable components, in Automata Studies, edited by G. Cuniberti, G. Fagas, and K. Richter, pages 329–378, Princeton Univeristy Press, Princeton, NJ, 1956.Google Scholar
  137. 137.
    S. Roy and V. Beiu, IEEE Trans. Nanotechnol. 4, 441 (2005).Google Scholar
  138. 138.
    E. Ahmed and J. Rose, IEEE Trans. VLSI 12, 288 (2004).Google Scholar
  139. 139.
    J. Kouloheris and A. E. Gamal, PLA-based FPA versus cell granularity, in Proc. of CICS’92, pages 4.3.1–4, Boston, MA, 1992.Google Scholar
  140. 140.
    V. A. Sverdlov, T. J. Walls, and K. K. Likharev, IEEE Trans. Electron Dev. 50, 1926 (2003).Google Scholar
  141. 141.
    W. D. Brown and J. Brewer, Nonvolatile semiconductor memory technology: a comprehensive guide to understanding and to using NVSM devices, IEEE Press series on microelectronic systems., IEEE Press, New York, 1998.Google Scholar
  142. 142.
    J. M. Rabaey, A. P. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, Pearson Education, Upper Saddle River, NJ, 2nd edition, 2003.Google Scholar
  143. 143.
    V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for deep-submicron FPGAs, Kluwer Int. Series in Eng. and Comp. Science 497, Kluwer Academic, Boston, London, 1999.Google Scholar
  144. 144.
    FPGA place-and-route challenge, 1999, Available online at \(\sim\)vaughn/challenge/ challenge.html/.
  145. 145.
    M. J. Flynn and S. F. Oberman, Advanced Computer Arithmetic Design, Wiley, New York, 2001.Google Scholar
  146. 146.
    K. K. Likharev and D. B. Strukov, Prospects for the development of digital CMOL circuits, in Proc. of NanoArch’07, pages 109–116, San Jose, CA, 2007.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • Dmitri B. Strukov
    • 1
  1. 1.Hewlett-Packard LaboratoriesPalo AltoUSA

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