Nano and Giga Challenges for Information Technology

  • R. Stanley Williams
Part of the Nanostructure Science and Technology book series (NST)

The primary technology driver for the integrated circuit industry and all of the information technology supported by that industry has been Moore’s law, the observation that the number of transistors on a chip has roughly doubled every 18 months over the past four decades. In concert with this exponential increase in transistors has come the dramatic increase in performance of integrated circuits while the cost of a single chip has remained fairly constant. This astounding improvement in a basic technology over a many-decade-long period is unprecedented and has led to a huge industry with a major economic footprint and enabled major increases in productivity and functionality for a wide variety of other sectors of society.

There have been many eras in the past when pundits have predicted the end of Moore’s scaling for a variety of excellent technical and engineering reasons. In all those cases, motivated engineers have overcome the barriers foreseen by the experts and kept the industry...


Functional Scaling Logic Circuit Entire Circuit Device Death Reliable Machine 
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  1. 1.
    J. von Neumann, “Probabilistic logics and the synthesis of reliable organisms from unreliable components” in C. E. Shannon and J. McCarthy, Eds. Automata Studies (1955), 43–98.Google Scholar
  2. 2.
    E. F. Moore and C. E. Shannon, “Reliable circuits using less reliable relays,” Journal of the Franklin Institute (1956), 191–208 and 281–297.Google Scholar
  3. 3.
    J. R. Heath, P. J. Kuekes, G. S. Snider and R. S. Williams, “A defect-tolerant computer architecture: Opportunities for nanotechnology,” Science 280 (1998), 1716.CrossRefGoogle Scholar
  4. 4.
    D. B. Strukov and K. K. Likharev, “CMOL FPGA: A cell-based, reconfigurable architecture for hybrid digital circuits using two-terminal nanodevices,” Nanotechnology 16 (2005), 888–900.CrossRefGoogle Scholar
  5. 5.
    G. S. Snider and R. S. Williams, “Nano/CMOS architectures using field-programmable nanowire interconnect,” Nanotechnology 18 (2007), art. no. 035204.Google Scholar
  6. 6.
    P. J. Kuekes, W. Robinett, G. Seroussi and R. S. Williams, “Defect-tolerant interconnect to nanoelectronic circuits: Internally redundant demultiplexers based on error-correcting codes,” Nanotechnology 16 (2005), 869–882.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • R. Stanley Williams
    • 1
  1. 1.Information and Quantum Systems LaboratoryHP Labs, Hewlett-Packard CompanyMS 1123, Palo Alto

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