Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
S.T. Ma, A. Keshavarzi, V. De, J.R. Brews, “A statistical model for extracting geometric sources of transistor performance variation,” IEEE Transactions on Electron Devices, Volume 51, Issue 1, pp. 36–41, January 2004.
R. Gonzalez, B. Gordon, and M. Horowitz, “Supply and threshold voltage scaling for low power CMOS,” IEEE Journal of Solid-State Circuits, Volume 32, Issue 8, August 1997.
S. Yokogawa,H. Takizawa, “Electromigration induced incubation, drift and threshold in single-damascene copper interconnects,” IEEE 2002 International Interconnect Technology Conference, 2002, pp. 127–129, 3–5 June 2002.
W. Jie and E. Rosenbaum, “Gate oxide reliability under ESD-like pulse stress,” IEEE Transactions on Electron Devices, Volume 51, Issue 7, July 2004.
International Technology Roadmap for Semiconductors, 2005 edition, http://www.itrs.net/ Links/2005ITRS/Home2005.htm.
M. Hashimoto, H. Onodera, “Increase in delay uncertainty by performance optimization,” IEEE International Symposium on Circuits and Systems, 2001, Volume 5, pp. 379–382, 5, 6–9 May 2001.
S. Rangan, N. Mielke and E. Yeh, “Universal recovery behavior of negative bias temperature instability,” IEEE Intl. Electron Devices Mtg., p. 341, December 2003.
G. Wolrich, E. McLellan, L. Harada, J. Montanaro, and R. Yodlowski, “A high performance floating point coprocessor,” IEEE Journal of Solid-State Circuits, Volume 19, Issue 5, October 1984.
Trasmeta Corporation, “LongRun Power Management,” http://www.trans-meta.com/tech/longrun2.html
Intel Corporation, “Intel Speedstep Technology,” http://www.intel.com/support/processors/mobile/pentiumiii/ss.htm
ARM Limited, http://www.arm.com/products/esd/iem_home.html
T. Burd, T. Pering, A. Stratakos, and R. Brodersen, “A dynamic voltage scaled microprocessor system,” International Solid-State Circuits Conference, February 2000.
A.K. Uht, “Going beyond worst-case specs with TEATime,” IEEE Micro Top Picks, pp. 51–56, 2004
K.J. Nowka, G.D. Carpenter, E.W. MacDonald, H.C. Ngo, B.C Brock, K.I. Ishii, T.Y. Nguyen and J.L. Burns, “A 32-bit powerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling,” IEEE Journal of Solid-State Circuits, Volume 37, Issue 11, pp. 1441–1447, November 2002
T.D. Burd, T.A. Pering, A.J. Stratakos and R.W. Brodersen, “A dynamic voltage scaled microprocessor system,” IEEE Journal of Solid-State Circuits, Volume 35, Issue 11, pp. 1571–1580, November 2000
Berkeley Wireless Research Center, http://bwrc.eecs.berkeley.edu/
M. Nakai, S. Akui, K. Seno, T. Meguro, T. Seki, T. Kondo, A. Hashiguchi, H. Kawahara, K. Kumano and M. Shimura, “Dynamic voltage and frequency management for a low power embedded microprocessor,” IEEE Journal of Solid-State Circuits, Volume 40, Issue 1, pp. 28–35, January. 2005
A. Drake, R. Senger, H. Deogun, G. Carpenter, S. Ghiasi, T. Ngyugen, N. James and M. Floyd, “A distributed critical-path timing monitor for a 65 nm high-performance microprocessor,” International Solid-State Circuits Conference, pp. 398–399, 2007.
T. Kehl, “Hardware self-tuning and circuit performance monitoring,” 1993 Int’l Conference on Computer Design (ICCD-93), October 1993.
S. Lu, “Speeding up processing with approximation circuits,” IEEE Micro Top Picks, pp. 67–73, 2004
T. Austin, V. Bertacco, D. Blaauw and T. Mudge, “Opportunities and challenges in better than worst-case design,” Proceedings of the ASP-DAC 2005, Volume 1, pp. 18–21, 2005.
C. Kim, D. Burger and S.W. Keckler, IEEE Micro, Volume 23, Issue 6, pp. 99–107, November–December 2003.
Z. Chishti, M.D. Powell, T. N. Vijaykumar, “Distance associativity for high-performance energy-efficient non-uniform cache architectures,” Proceedings of the International Symposium on Microarchitecture, 2003, MICRO-36
F. Worm, P. Ienne and P. Thiran, “A robust self-calibrating transmission scheme for on-chip networks,” IEEE Transactions on Very Large Scale Integration, Volume 13, Issue 1, January 2005.
R. Hegde and N. R. Shanbhag, “A voltage overscaled low-power digital filter IC,” IEEE Journal of Solid-State Circuits, Volume39, Issue 2, February 2004.
D. Roberts, T. Austin, D. Blaauw, T. Mudge and K. Flautner, “Error analysis for the support of robust voltage scaling,” International Symposium on Quality Electronic Design (ISQED), 2005.
L. Anghel and M. Nicolaidis, “Cost reduction and evaluation of a temporary faults detecting technique,” Proceedings of Design, Automation and Test in Europe Conference and Exhibition 2000, 27–30 March 2000 pp. 591–598
S. Das, D. Roberts, S. Lee, S. Pant, D. Blaauw, T. Austin, T. Mudge, K. Flautner, “A self-tuning DVS processor using delay-error detection and correction,” IEEE Journal of Solid-State Circuits, pp. 792–804, April 2006.
R. Sproull, I. Sutherland, and C. Molnar, “Counterflow pipeline processor architecture,” Sun Microsystems Laboratories Inc. Technical Report SMLI-TR-94-25, April 1994.
W. Dally, J. Poulton, Digital System Engineering, Cambridge University Press, 1998
D. Blaauw, S.Kalaiselvam, K. Lai, W.Ma, S. Pant, C. Tokunaga, S. Das and D.Bull “RazorII: In-situ error detection and correction for PVT and SER tolerance,” International Solid-State Circuits Conference, 2008
D. Ernst, N. S. Kim, S. Das, S. Pant, T. Pham, R. Rao, C. Ziesler, D. Blaauw, T. Austin, T. Mudge, K. Flautner, “Razor: A low-power pipeline based on circuit-level timing speculation,” Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 7–18, December 2003.
A. Asenov, S. Kaya, A.R. Brown, “Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness,” IEEE Transactions on Electron Devices, Volume 50, Issue 5, pp. 1254–1260, May 2003.
K. Ogata, “Modern control engineering,” 4th edition, Prentice Hall, New Jersey, 2002.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2008 Springer Science+Business Media, LLC
About this chapter
Cite this chapter
Das, S., Roberts, D., Blaauw, D., Bull, D., Mudge, T. (2008). Architectural Techniques for Adaptive Computing. In: Wang, A., Naffziger, S. (eds) Adaptive Techniques for Dynamic Processor Optimization. Series on Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-76472-6_8
Download citation
DOI: https://doi.org/10.1007/978-0-387-76472-6_8
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-76471-9
Online ISBN: 978-0-387-76472-6
eBook Packages: EngineeringEngineering (R0)