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The Challenges of Testing Adaptive Designs

  • Eric Fetzer
  • Jason Stinson
  • Brian Cherkauer
  • Steve Poehlman
Part of the Series on Integrated Circuits and Systems book series (ICIR)

In this chapter, we describe the adaptive techniques used in the Itanium® 2 9000 series microprocessor previously known as Montecito [1].

Montecito features two dual-threaded cores with over 26.5 MB of total on die cache in a 90 nm process technology [ 2] with seven layers of copper interconnect. The die, shown in Figure 12.1, is 596 mm 2in size, contains 1.72 billion transistors, and consumes 104 W at a maximum frequency of 1.6 GHz. To manufacture a product of such complexity, a sophisticated series of tests are performed on each part to ensure reliable operation throughout its service at a customer installation. Adaptive features often interfere with these tests. This chapter discusses three adaptive features on Montecito: active de-skew for reliable low skew clocks, Cache Safe Technology® for robust cache operation, and Foxton Technology® for power management. Traditional test methods are discussed, and the specific impacts of active de-skew and the power measurement system for...

Keywords

Delay Line Power Measurement Error Correction Code Soft Error Voltage Droop 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • Eric Fetzer
  • Jason Stinson
  • Brian Cherkauer
  • Steve Poehlman

There are no affiliations available

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