Advertisement

Dynamic and Adaptive Techniques in SRAM Design

  • John J. Wuu
Part of the Series on Integrated Circuits and Systems book series (ICIR)

Introduction

The International Technology Roadmap for Semiconductors (ITRS) predicted in 2001 that by 2013, over 90% of SOC die area will be occupied by memory [7]. Such level of integration poses many challenges, such as power, reliability, and yield. In addition, as transistor dimensions continue to shrink, transistor threshold voltage (VT) variation, which is inversely proportional to the square root of the transistor area, continues to increase. This VTvariation, along with other factors contributing to overall variation, is creating difficulties in designing stable SRAM cells that meet product density and voltage requirements.

This chapter examines various dynamic and adaptive techniques for mitigating some of these common challenges in SRAM design. The chapter first introduces innovations at the bitslice level, which includes SRAM cells and immediate peripheral circuitry. These innovations seek to improve bitcell stability and increase the read and write margins, while reducing...

Keywords

Source Line Power Saving Error Correct Code Storage Node Read Operation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. [1]
    Agarwal A, Roy, K (2003) A Noise Tolerant Cache Design to Reduce Gate and Sub-threshold Leakage in the Nanometer Regime. Proc. ISLPED, pp 18–21Google Scholar
  2. [2]
    Agarwal A, Paul B, Roy K (2004) A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies. Proc. IOLTS, pp 149–154Google Scholar
  3. [3]
    Bhavnagarwala A, Kosonocky S, Kowalczyk S, Joshi R, Chan Y, Srinivasan U, Wadhwa J (2004) A Transregional CMOS SRAM with Single, Logic VDD and Dynamic Power Rails. Symp. VLSI Circuits Dig. Tech. Papers, pp 292–293Google Scholar
  4. [4]
    Chang J, Huang M, Shoemaker J, Benoit J, Chen SL, Chen W, Chiu S, Ganesan R, Leong G, Lukka V, Rusu S, Srivastava D (2007) The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series. IEEE J. Solid-State Circuits vol 42 no 4, pp 846–852CrossRefGoogle Scholar
  5. [5]
    Cheng W, Pedram M (2001) Memory Bus Encoding for Low Power: A Tutorial. Proc. ISQED, pp 26–28Google Scholar
  6. [6]
    Dorsey J, Searles S, Ciraula M, Johnson S, Bujanos N, Wu D, Braganza M, Meyers S, Fang E, Kumar R (2007) An Integrated Quad-Core Opteron Processor. ISSCC Dig. Tech. Papers, pp 102–103Google Scholar
  7. [7]
    International Technology Roadmap for Semiconductors (2001)Google Scholar
  8. [8]
    Jumel F, Royannez P, Mair H, Scott D, Er Rachidi A, Lagerquist R, Chau M, Gururajarao S, Thiruvengadam S, Clinton M, Menezes V, Hollingsworth R, Vaccani J, Piacibello F, Culp N, Rosal J, Ball M, Ben-Amar F, Bouetel L, Domerego O, Lachese JL, Fournet-Fayard C, Ciroux J, Raibaut C, Ko U (2006) A Leakage Management System Based on Clock Gating Infrastructure for a 65-nm Digital Base-Band Modem Chip. Symp. VLSI Circuits Dig. Tech. Papers, pp 214–215Google Scholar
  9. [9]
    Kaxiras S, Hu Z (2001) Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power. Int. Symp. Comput. Architect., pp 240–25Google Scholar
  10. [10]
    Khellah M, Kim SN, Howard J, Ruhl G, Sunna M, Ye Y, Tschanz J, Somasekhar D, Borkar N, Hamzaoglu F, Pandya G, Farhang A, Zhang K, De V (2006) A 4.2 GHz 0.3 mm2 256 kb Dual-Vcc SRAM Building Block in 65 nm CMOS. ISSCC Dig. Tech. Papers, pp 2572–2573Google Scholar
  11. [11]
    Khellah M, Ye Y, Kim NS, Somasekhar D, Pandya G, Farhang A, Zhang K, Webb C, De V (2006) Wordline & Bitline Pulsing Schemes for Improving SRAM Cell Stability in Low-Vcc 65 nm CMOS Designs. Symp. VLSI Circuits Dig. Tech. Papers, pp 9–10Google Scholar
  12. [12]
    Kim C, Kim JJ, Chang IJ, Roy K (2006) PVT-Aware Leakage Reduction for On-Die Caches With Improved Read Stability. IEEE J. Solid-State Circuits vol 41 no 1, pp 170–178CrossRefGoogle Scholar
  13. [13]
    Mizuno H, NaganoT (1995) Driving Source-Line (DSL) Cell Architecture for Sub-1-V High-Speed Low-Power Application. Symp. VLSI Circuits Dig. Tech. Papers, pp 25–26Google Scholar
  14. [14]
    Ohbayashi S, Yabuuchi M, Nii K, Tsukamoto Y, Imaoka S, Oda Y, Yoshihara T, Igarashi M, Takeuchi M, Kawashima H, Yamaguchi Y, Tsukamoto K, Inuishi M, Makino H, Ishibashi K, Shinohara H (2007) A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits. IEEE J. Solid-State Circuits vol 42 no 4, pp 820–829CrossRefGoogle Scholar
  15. [15]
    Osada K, Shin JL, Khan M, Liou Y, Wang K, Shoji K, Kuroda K, Ikeda S, Ishibashi K (2001) Universal-Vdd 0.65-2.0-V 32-kB Cache Using a Voltage-Adapted Timing-Generation Scheme and a Lithographically Symmetrical Cell. IEEE J. Solid-State Circuits vol 36 no 11, pp 1738–1744CrossRefGoogle Scholar
  16. [16]
    Sakran N, Yuffe M, Mehalel M, Doweck J, Knoll E, Kovacs A (2007) The Implementation of the 65 nm Dual-Core 64b Merom Processor. ISSCC Dig. Tech. Papers, pp 106–107Google Scholar
  17. [17]
    Seevinck E, List FJ, Lohstroh J (1987) Static-Noise Margin Analysis of MOS SRAM Cells. IEEE J. Solid-State Circuits vol 22 no 5, pp 748–754CrossRefGoogle Scholar
  18. [18]
    Takeyama Y, Otake H, Hirabayashi O, Kushida K, Otsuka N (2006) A Low Leakage SRAM Macro With Replica Cell Biasing Scheme. IEEE J. Solid-State Circuits vol 41 no 4, pp 815–822CrossRefGoogle Scholar
  19. [19]
    Wuu J, Weiss D, Morganti C, Dreesen M (2005) The Asynchronous 24 MB On-chip Level-3 Cache for a Dual-core Itanium Family Processor. ISSCC Dig. Tech. Papers, pp 488–489Google Scholar
  20. [20]
    Yamaoka M, Shinozaki Y, Maeda N, Shimazaki Y, Kato K, Shimada S, Yanagisawa K, Osada K (2004) A 300 MHz 25uA/Mb Leakage On-Chip SRAM Module Featuring Process-Variation Immunity and Low-Leakage-Active Mode for Mobile-Phone-Application Processor. ISSCC Dig. Tech. Papers, pp 494–495Google Scholar
  21. [21]
    Yamaoka M, Maeda N, Shinozaki Y, Shimazaki Y, Nii K, Shimada S, Yanagisawa K, Kawahara T (2006) 90-nm Process-Variation Adaptive Embedded SRAM Modules With Power-Line-Floating Write Technique. IEEE J. Solid-State Circuits vol 41 no 3, pp 705–711CrossRefGoogle Scholar
  22. [22]
    Zhang K, Bhattacharya U, Chen Z, Hamzaoglu F, Murray D, Vallepalli N, Wang Y, Zheng B, Bohr M (2006) A 3-GHz 70-Mb SRAM in 65-nm CMOS Technology With Integrated Column-Based Dynamic Power Supply. IEEE J. Solid-State Circuits vol 41 no 1, pp 146–151CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • John J. Wuu
    • 1
  1. 1.Advanced Micro Devices, Inc.USA

Personalised recommendations