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Temporal Adaptation – Asynchronicity in Processor Design

  • Steve Furber
  • Jim Garside
Part of the Series on Integrated Circuits and Systems book series (ICIR)

Introduction

Throughout most of the history of the microprocessor, designers have employed an approach based on the use of a central clock to control functional units within the processor. While there are situations – such as the musicians in a symphony orchestra or the crew of a rowing boat – where global synchrony is a vital aspect of the overall functionality, a microprocessor is not such a system. Here the clock is merely a design convenience, a constraint on how the system’s components operate that simplifies some design issues and allows the use of a well-developed VLSI design flow where the designer can analyse the entire system state at any instant and use this to influence the transition to the next state. The clock has become so dominant in modern processor design that few designers ever stop to consider dispensing with it; however, it is not necessary – synchronisation may be restricted to places where it is essential to function.

Although a tremendous aid in simplifying a...

References

  1. [1]
    A.J. Martin, S.M. Burns, T.K. Lee, D. Borkovic and P.J. Hazewindus, “The Design of an Asynchronous Microprocessor”, ARVLSI: Decennial Caltech Conference on VLSI, ed. C.L. Seitz, MIT Press, 1989, pp. 351–373.Google Scholar
  2. [2]
    S.B. Furber, P. Day, J.D. Garside, N.C. Paver and J.V. Woods, “AMULET1: A Micropipelined ARM”, Proceedings of CompCon'94, IEEE Computer Society Press, San Francisco, March 1994, pp.476–485.Google Scholar
  3. [3]
    A. Takamura, M. Kuwako, M. Imai, T. Fujii, M. Ozawa, I. Fukasaku, Y. Ueno and T. Nanya, “TITAC-2: A 32-Bit Asynchronous Microprocessor Based on Scalable-Delay-Insensitive Model”, Proceedings of ICCD'97, October 1997, pp. 288–294.Google Scholar
  4. [4]
    M. Renaudin, P. Vivet and F. Robin, “ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor”, Proceedings of Async'98, IEEE Computer Society, 1998, pp. 22–31. ISBN:0-8186-8392-9.Google Scholar
  5. [5]
    S.B. Furber, J.D. Garside and D.A. Gilbert, “AMULET3: A High-Performance Self-Timed ARM Microprocessor”, Proceedings of ICCD'98, Austin, TX, 5–7 October 1998, pp. 247–252. ISBN 0-8186-9099-2.Google Scholar
  6. [6]
    S.B. Furber, A. Efthymiou, J.D. Garside, M.J.G. Lewis, D.W. Lloyd and S. Temple, “Power Management in the AMULET Microprocessors”, IEEE Design and Test of Computers, ed. E. Macii, March–April 2001, Vol. 18, No. 2, pp. 42–52. ISSN: 0740-7475.Google Scholar
  7. [7]
    H. van Gageldonk, K. van Berkel, A. Peeters, D. Baumann, D. Gloor and G. Stegmann, “An Asynchronous Low-Power 80C51 Microcontroller”, Proceedings of Async'98, IEEE Computer Society, 1998, pp. 96–107. ISBN:0-8186-8392-9.Google Scholar
  8. [8]
    A. Bink and R. York, “ARM996HS: The First Licensable, Clockless 32-Bit Processor Core”, IEEE Micro, March 2007, Vol. 27, No. 2, pp. 58–68. ISSN: 0272-1732.CrossRefGoogle Scholar
  9. [9]
    I. Sutherland, “Micropipelines”, Communications of the ACM, June 1989, Vol. 32, No. 6, pp.720–738. ISSN: 0001-0782.CrossRefGoogle Scholar
  10. [10]
    J. Sparsø and S. Furber (eds.), “Principles of Asynchronous Circuit Design – A Systems Perspective”, Kluwer Academic Publishers, 2002. ISBN-10: 0792376137 ISBN-13: 978-0792376132.Google Scholar
  11. [11]
    S.B. Furber, D.A. Edwards and J.D. Garside, “AMULET3: A 100 MIPS Asynchronous Embedded Processor”, Proceedings of ICCD'00, 17–20 September 2000.Google Scholar
  12. [12]
    D. Seal (ed.), “ARM Architecture Reference Manual (Second Edition)”, Addison-Wesley, 2000. ISBN-10: 0201737191 ISBN-13: 978-0201737196.Google Scholar
  13. [13]
    J.D. Garside, “A CMOS VLSI Implementation of an Asynchronous ALU”,“Asynchronous Design Methodologies”, eds. S.B. Furber and M. Edwards, Elsevier 1993, IFIP Trans. A-28, pp. 181–207.Google Scholar
  14. [14]
    D. Hormdee and J.D. Garside, “AMULET3i Cache Architecture”, Proceedings of Async’01, IEEE Computer Society Press, March 2001, pp. 152–161. ISSN 1522-8681 ISBN 0-7695-1034-4.Google Scholar
  15. [15]
    W.A. Clark, “Macromodular Computer Systems”, Proceedings of the Spring Joint Conference, AFIPS, April 1967.Google Scholar
  16. [16]
    D.M. Chapiro, “Globally-Asynchronous Locally-Synchronous Systems”, Ph.D. thesis, Stanford University, USA, October 1984.Google Scholar
  17. [17]
    M. Lewis, J.D. Garside and L.E.M. Brackenbury, “Reconfigurable Latch Controllers for Low Power Asynchronous Circuits”, Proceedings of Async'99, IEEE Computer Society Press, April 1999, pp. 27–35.Google Scholar
  18. [18]
    A. Efthymiou, “Asynchronous Techniques for Power-Adaptive Processing”, Ph.D. thesis, Department of Computer Science, University of Manchester, UK, 2002.Google Scholar
  19. [19]
    A. Efthymiou and J.D. Garside, “Adaptive Pipeline Depth Control for Processor Power-Management”, Proceedings of ICCD'02, Freiburg, September 2002, pp. 454–457. ISBN 0-7695 1700-5 ISSN 1063-6404.Google Scholar
  20. [20]
    A. Efthymiou and J.D. Garside, “Adaptive Pipeline Structures for Speculation Control”, Proceedings of Async'03, Vancouver, May 2003, pp. 46–55. ISBN 0-7695-1898-2 ISSN 1522-8681.Google Scholar
  21. [21]
    W.S. Coates, J.K. Lexau, I.W. Jones, S.M. Fairbanks and I.E. Sutherland, “FLEETzero: An Asynchronous Switching Experiment”, Proceedings of Async'01, IEEE Computer Society, 2001, pp. 173–182. ISBN:0-7695-1034-5.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • Steve Furber
    • 1
  • Jim Garside
    • 1
  1. 1.The University of ManchesterUK

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