Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise is increasing. The supply noise is much larger during at-speed delay test compared to normal circuit operation since large number of transitions occur within a short time frame. Existing commercial ATPG tools do not consider the excessive supply noise that might occur in the design during test pattern generation. This chapter presents two case studies of an ITC'99 benchmark and a SOC design to show detailed IR-drop analysis, measurement and its effects on design performance during at-speed test. Next, a method is presented to measure the average power of at-speed test patterns, referred to as switching cycle average power (SCAP). Using SCAP model provides a cost-effective solution to identify patterns with high IR-drop and avoids expensive dynamic IR-drop analysis. A new practical pattern generation procedure is presented to generate supply noise tolerant delay test patterns using existing capabilities in commercial ATPG tools. The procedure will be implemented on two large designs. The results demonstrate that the new patterns, while slightly larger, will minimize the supply noise effects on path delay.
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(2008). IR-drop Tolerant At-speed Test Pattern Generation. In: Nanometer Technology Designs High-Quality Delay Tests. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-75728-5_9
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